1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 34 #ifdef CFG_WITH_NSEC_UARTS 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 43 #endif 44 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 56 57 static void main_fiq(void); 58 59 static const struct thread_handlers handlers = { 60 .std_smc = tee_entry_std, 61 .fast_smc = tee_entry_fast, 62 .nintr = main_fiq, 63 .cpu_on = pm_panic, 64 .cpu_off = pm_panic, 65 .cpu_suspend = pm_panic, 66 .cpu_resume = pm_panic, 67 .system_off = pm_panic, 68 .system_reset = pm_panic, 69 }; 70 71 const struct thread_handlers *generic_boot_get_handlers(void) 72 { 73 return &handlers; 74 } 75 76 #define _ID2STR(id) (#id) 77 #define ID2STR(id) _ID2STR(id) 78 79 static TEE_Result platform_banner(void) 80 { 81 #ifdef CFG_EMBED_DTB 82 IMSG("Platform stm32mp1: flavor %s - DT %s", 83 ID2STR(PLATFORM_FLAVOR), 84 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 85 #else 86 IMSG("Platform stm32mp1: flavor %s - no device tree", 87 ID2STR(PLATFORM_FLAVOR)); 88 #endif 89 90 return TEE_SUCCESS; 91 } 92 service_init(platform_banner); 93 94 /* 95 * Console 96 * 97 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 98 * trace console. Value 0 disables the early console. 99 * 100 * We cannot use the generic serial_console support since probing 101 * the console requires the platform clock driver to be already 102 * up and ready which is done only once service_init are completed. 103 */ 104 static struct stm32_uart_pdata console_data; 105 106 void console_init(void) 107 { 108 /* Early console initialization before MMU setup */ 109 struct uart { 110 paddr_t pa; 111 bool secure; 112 } uarts[] = { 113 [0] = { .pa = 0 }, 114 [1] = { .pa = USART1_BASE, .secure = true, }, 115 [2] = { .pa = USART2_BASE, .secure = false, }, 116 [3] = { .pa = USART3_BASE, .secure = false, }, 117 [4] = { .pa = UART4_BASE, .secure = false, }, 118 [5] = { .pa = UART5_BASE, .secure = false, }, 119 [6] = { .pa = USART6_BASE, .secure = false, }, 120 [7] = { .pa = UART7_BASE, .secure = false, }, 121 [8] = { .pa = UART8_BASE, .secure = false, }, 122 }; 123 124 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 125 assert(!cpu_mmu_enabled()); 126 127 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 128 return; 129 130 /* No clock yet bound to the UART console */ 131 console_data.clock = DT_INFO_INVALID_CLOCK; 132 133 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 134 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 135 136 register_serial_console(&console_data.chip); 137 138 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 139 } 140 141 #ifdef CFG_DT 142 static TEE_Result init_console_from_dt(void) 143 { 144 struct stm32_uart_pdata *pd = NULL; 145 void *fdt = NULL; 146 int node = 0; 147 TEE_Result res = TEE_ERROR_GENERIC; 148 149 fdt = get_embedded_dt(); 150 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 151 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 152 fdt = get_external_dt(); 153 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 154 if (res == TEE_ERROR_ITEM_NOT_FOUND) 155 return TEE_SUCCESS; 156 if (res != TEE_SUCCESS) 157 return res; 158 } 159 160 pd = stm32_uart_init_from_dt_node(fdt, node); 161 if (!pd) { 162 IMSG("DTB disables console"); 163 register_serial_console(NULL); 164 return TEE_SUCCESS; 165 } 166 167 /* Replace early console with the new one */ 168 console_flush(); 169 console_data = *pd; 170 free(pd); 171 register_serial_console(&console_data.chip); 172 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 173 174 return TEE_SUCCESS; 175 } 176 177 /* Probe console from DT once clock inits (service init level) are completed */ 178 service_init_late(init_console_from_dt); 179 #endif 180 181 /* 182 * GIC init, used also for primary/secondary boot core wake completion 183 */ 184 static struct gic_data gic_data; 185 186 static void main_fiq(void) 187 { 188 gic_it_handle(&gic_data); 189 } 190 191 void main_init_gic(void) 192 { 193 assert(cpu_mmu_enabled()); 194 195 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 196 itr_init(&gic_data.chip); 197 198 stm32mp_register_online_cpu(); 199 } 200 201 void main_secondary_init_gic(void) 202 { 203 gic_cpu_init(&gic_data); 204 205 stm32mp_register_online_cpu(); 206 } 207 208 #ifndef CFG_EMBED_DTB 209 static TEE_Result init_stm32mp1_drivers(void) 210 { 211 /* Without secure DTB support, some drivers must be inited */ 212 stm32_etzpc_init(ETZPC_BASE); 213 214 return TEE_SUCCESS; 215 } 216 driver_init(init_stm32mp1_drivers); 217 #endif /*!CFG_EMBED_DTB*/ 218 219 /* Platform initializations once all drivers are ready */ 220 static TEE_Result init_late_stm32mp1_drivers(void) 221 { 222 /* Secure internal memories for the platform, once ETZPC is ready */ 223 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 224 etzpc_lock_tzma(0); 225 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 226 etzpc_lock_tzma(1); 227 228 /* Static secure DECPROT configuration */ 229 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 230 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 231 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 232 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 233 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 234 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 235 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 236 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 237 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 238 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 239 /* Static non-secure DECPROT configuration */ 240 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 241 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 242 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 243 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 244 /* Release few resource to the non-secure world */ 245 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 246 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 247 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 248 249 return TEE_SUCCESS; 250 } 251 driver_init_late(init_late_stm32mp1_drivers); 252 253 vaddr_t get_gicc_base(void) 254 { 255 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 256 257 return io_pa_or_va_secure(&base); 258 } 259 260 vaddr_t get_gicd_base(void) 261 { 262 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 263 264 return io_pa_or_va_secure(&base); 265 } 266 267 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 268 { 269 cfg->base = BSEC_BASE; 270 cfg->upper_start = STM32MP1_UPPER_OTP_START; 271 cfg->max_id = STM32MP1_OTP_MAX_ID; 272 cfg->closed_device_id = DATA0_OTP; 273 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 274 } 275 276 uint32_t may_spin_lock(unsigned int *lock) 277 { 278 if (!lock || !cpu_mmu_enabled()) 279 return 0; 280 281 return cpu_spin_lock_xsave(lock); 282 } 283 284 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 285 { 286 if (!lock || !cpu_mmu_enabled()) 287 return; 288 289 cpu_spin_unlock_xrestore(lock, exceptions); 290 } 291 292 static vaddr_t stm32_tamp_base(void) 293 { 294 static struct io_pa_va base = { .pa = TAMP_BASE }; 295 296 return io_pa_or_va_secure(&base); 297 } 298 299 static vaddr_t bkpreg_base(void) 300 { 301 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 302 } 303 304 vaddr_t stm32mp_bkpreg(unsigned int idx) 305 { 306 return bkpreg_base() + (idx * sizeof(uint32_t)); 307 } 308 309 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 310 { 311 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 312 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 313 314 /* Get non-secure mapping address for GPIOZ */ 315 if (bank == GPIO_BANK_Z) 316 return io_pa_or_va_nsec(&gpioz_base); 317 318 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 319 assert(bank <= GPIO_BANK_K); 320 321 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 322 } 323 324 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 325 { 326 if (bank == GPIO_BANK_Z) 327 return 0; 328 329 assert(bank <= GPIO_BANK_K); 330 return bank * GPIO_BANK_OFFSET; 331 } 332 333 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 334 { 335 if (bank == GPIO_BANK_Z) 336 return GPIOZ; 337 338 assert(bank <= GPIO_BANK_K); 339 return GPIOA + bank; 340 } 341