1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <mm/core_memprot.h> 16 #include <platform_config.h> 17 #include <sm/psci.h> 18 #include <tee/entry_std.h> 19 #include <tee/entry_fast.h> 20 21 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CONSOLE_UART_SIZE); 22 23 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 24 register_phys_mem(MEM_AREA_IO_SEC, BKP_REGS_BASE, SMALL_PAGE_SIZE); 25 26 static struct gic_data gic_data; 27 static struct console_pdata console_data; 28 29 static void main_fiq(void) 30 { 31 gic_it_handle(&gic_data); 32 } 33 34 static const struct thread_handlers handlers = { 35 .std_smc = tee_entry_std, 36 .fast_smc = tee_entry_fast, 37 .nintr = main_fiq, 38 .cpu_on = pm_panic, 39 .cpu_off = pm_panic, 40 .cpu_suspend = pm_panic, 41 .cpu_resume = pm_panic, 42 .system_off = pm_panic, 43 .system_reset = pm_panic, 44 }; 45 46 const struct thread_handlers *generic_boot_get_handlers(void) 47 { 48 return &handlers; 49 } 50 51 void console_init(void) 52 { 53 stm32_uart_init(&console_data, CONSOLE_UART_BASE); 54 register_serial_console(&console_data.chip); 55 } 56 57 void main_init_gic(void) 58 { 59 void *gicc_base; 60 void *gicd_base; 61 62 gicc_base = phys_to_virt(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 63 gicd_base = phys_to_virt(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 64 if (!gicc_base || !gicd_base) 65 panic(); 66 67 gic_init(&gic_data, (vaddr_t)gicc_base, (vaddr_t)gicd_base); 68 itr_init(&gic_data.chip); 69 } 70 71 void main_secondary_init_gic(void) 72 { 73 gic_cpu_init(&gic_data); 74 } 75 76 /* 77 * SMP boot support and access to the mailbox 78 */ 79 #define GIC_SEC_SGI_0 8 80 81 static vaddr_t bckreg_base(void) 82 { 83 static void *va; 84 85 if (!cpu_mmu_enabled()) 86 return BKP_REGS_BASE + BKP_REGISTER_OFF; 87 88 if (!va) 89 va = phys_to_virt(BKP_REGS_BASE + BKP_REGISTER_OFF, 90 MEM_AREA_IO_SEC); 91 92 return (vaddr_t)va; 93 } 94 95 static uint32_t *bckreg_address(unsigned int idx) 96 { 97 return (uint32_t *)bckreg_base() + idx; 98 } 99 100 static void release_secondary_early_hpen(size_t pos) 101 { 102 uint32_t *p_entry = bckreg_address(BCKR_CORE1_BRANCH_ADDRESS); 103 uint32_t *p_magic = bckreg_address(BCKR_CORE1_MAGIC_NUMBER); 104 105 *p_entry = TEE_LOAD_ADDR; 106 *p_magic = BOOT_API_A7_CORE1_MAGIC_NUMBER; 107 108 dmb(); 109 isb(); 110 itr_raise_sgi(GIC_SEC_SGI_0, BIT(pos)); 111 } 112 113 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 114 { 115 size_t pos = get_core_pos_mpidr(core_id); 116 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 117 118 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 119 return PSCI_RET_INVALID_PARAMETERS; 120 121 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 122 123 if (core_is_released[pos]) { 124 DMSG("core %zu already released", pos); 125 return PSCI_RET_DENIED; 126 } 127 core_is_released[pos] = true; 128 129 generic_boot_set_core_ns_entry(pos, entry, context_id); 130 release_secondary_early_hpen(pos); 131 132 return PSCI_RET_SUCCESS; 133 } 134