1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32mp1_etzpc.h> 12 #include <drivers/stm32_uart.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/dt.h> 15 #include <kernel/generic_boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 #ifdef CFG_WITH_NSEC_GPIOS 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 31 #endif 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 35 #ifdef CFG_WITH_NSEC_UARTS 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 44 #endif 45 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 57 58 #if DDR_BASE < CFG_TZDRAM_START 59 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 60 #endif 61 62 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 63 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 64 65 #if DRAM_END > TZDRAM_END 66 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 67 #endif 68 69 static const struct thread_handlers handlers = { 70 .cpu_on = pm_panic, 71 .cpu_off = pm_panic, 72 .cpu_suspend = pm_panic, 73 .cpu_resume = pm_panic, 74 .system_off = pm_panic, 75 .system_reset = pm_panic, 76 }; 77 78 const struct thread_handlers *generic_boot_get_handlers(void) 79 { 80 return &handlers; 81 } 82 83 #define _ID2STR(id) (#id) 84 #define ID2STR(id) _ID2STR(id) 85 86 static TEE_Result platform_banner(void) 87 { 88 #ifdef CFG_EMBED_DTB 89 IMSG("Platform stm32mp1: flavor %s - DT %s", 90 ID2STR(PLATFORM_FLAVOR), 91 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 92 #else 93 IMSG("Platform stm32mp1: flavor %s - no device tree", 94 ID2STR(PLATFORM_FLAVOR)); 95 #endif 96 97 return TEE_SUCCESS; 98 } 99 service_init(platform_banner); 100 101 /* 102 * Console 103 * 104 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 105 * trace console. Value 0 disables the early console. 106 * 107 * We cannot use the generic serial_console support since probing 108 * the console requires the platform clock driver to be already 109 * up and ready which is done only once service_init are completed. 110 */ 111 static struct stm32_uart_pdata console_data; 112 113 void console_init(void) 114 { 115 /* Early console initialization before MMU setup */ 116 struct uart { 117 paddr_t pa; 118 bool secure; 119 } uarts[] = { 120 [0] = { .pa = 0 }, 121 [1] = { .pa = USART1_BASE, .secure = true, }, 122 [2] = { .pa = USART2_BASE, .secure = false, }, 123 [3] = { .pa = USART3_BASE, .secure = false, }, 124 [4] = { .pa = UART4_BASE, .secure = false, }, 125 [5] = { .pa = UART5_BASE, .secure = false, }, 126 [6] = { .pa = USART6_BASE, .secure = false, }, 127 [7] = { .pa = UART7_BASE, .secure = false, }, 128 [8] = { .pa = UART8_BASE, .secure = false, }, 129 }; 130 131 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 132 133 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 134 return; 135 136 /* No clock yet bound to the UART console */ 137 console_data.clock = DT_INFO_INVALID_CLOCK; 138 139 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 140 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 141 142 register_serial_console(&console_data.chip); 143 144 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 145 } 146 147 #ifdef CFG_DT 148 static TEE_Result init_console_from_dt(void) 149 { 150 struct stm32_uart_pdata *pd = NULL; 151 void *fdt = NULL; 152 int node = 0; 153 TEE_Result res = TEE_ERROR_GENERIC; 154 155 fdt = get_embedded_dt(); 156 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 157 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 158 fdt = get_external_dt(); 159 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 160 if (res == TEE_ERROR_ITEM_NOT_FOUND) 161 return TEE_SUCCESS; 162 if (res != TEE_SUCCESS) 163 return res; 164 } 165 166 pd = stm32_uart_init_from_dt_node(fdt, node); 167 if (!pd) { 168 IMSG("DTB disables console"); 169 register_serial_console(NULL); 170 return TEE_SUCCESS; 171 } 172 173 /* Replace early console with the new one */ 174 console_flush(); 175 console_data = *pd; 176 free(pd); 177 register_serial_console(&console_data.chip); 178 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 179 180 return TEE_SUCCESS; 181 } 182 183 /* Probe console from DT once clock inits (service init level) are completed */ 184 service_init_late(init_console_from_dt); 185 #endif 186 187 /* 188 * GIC init, used also for primary/secondary boot core wake completion 189 */ 190 static struct gic_data gic_data; 191 192 void itr_core_handler(void) 193 { 194 gic_it_handle(&gic_data); 195 } 196 197 void main_init_gic(void) 198 { 199 assert(cpu_mmu_enabled()); 200 201 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 202 itr_init(&gic_data.chip); 203 204 stm32mp_register_online_cpu(); 205 } 206 207 void main_secondary_init_gic(void) 208 { 209 gic_cpu_init(&gic_data); 210 211 stm32mp_register_online_cpu(); 212 } 213 214 #ifndef CFG_EMBED_DTB 215 static TEE_Result init_stm32mp1_drivers(void) 216 { 217 /* Without secure DTB support, some drivers must be inited */ 218 stm32_etzpc_init(ETZPC_BASE); 219 220 return TEE_SUCCESS; 221 } 222 driver_init(init_stm32mp1_drivers); 223 #endif /*!CFG_EMBED_DTB*/ 224 225 /* Platform initializations once all drivers are ready */ 226 static TEE_Result init_late_stm32mp1_drivers(void) 227 { 228 /* Secure internal memories for the platform, once ETZPC is ready */ 229 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 230 etzpc_lock_tzma(0); 231 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 232 etzpc_lock_tzma(1); 233 234 /* Static secure DECPROT configuration */ 235 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 236 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 237 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 238 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 239 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 240 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 241 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 242 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 243 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 244 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 245 /* Static non-secure DECPROT configuration */ 246 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 247 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 248 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 249 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 250 /* Release few resource to the non-secure world */ 251 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 252 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 253 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 254 255 return TEE_SUCCESS; 256 } 257 driver_init_late(init_late_stm32mp1_drivers); 258 259 vaddr_t get_gicc_base(void) 260 { 261 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 262 263 return io_pa_or_va_secure(&base); 264 } 265 266 vaddr_t get_gicd_base(void) 267 { 268 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 269 270 return io_pa_or_va_secure(&base); 271 } 272 273 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 274 { 275 cfg->base = BSEC_BASE; 276 cfg->upper_start = STM32MP1_UPPER_OTP_START; 277 cfg->max_id = STM32MP1_OTP_MAX_ID; 278 cfg->closed_device_id = DATA0_OTP; 279 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 280 } 281 282 bool stm32mp_is_closed_device(void) 283 { 284 uint32_t otp = 0; 285 TEE_Result result = TEE_ERROR_GENERIC; 286 287 /* Non closed_device platform expects fuse well programmed to 0 */ 288 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 289 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 290 return false; 291 292 return true; 293 } 294 295 uint32_t may_spin_lock(unsigned int *lock) 296 { 297 if (!lock || !cpu_mmu_enabled()) 298 return 0; 299 300 return cpu_spin_lock_xsave(lock); 301 } 302 303 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 304 { 305 if (!lock || !cpu_mmu_enabled()) 306 return; 307 308 cpu_spin_unlock_xrestore(lock, exceptions); 309 } 310 311 static vaddr_t stm32_tamp_base(void) 312 { 313 static struct io_pa_va base = { .pa = TAMP_BASE }; 314 315 return io_pa_or_va_secure(&base); 316 } 317 318 static vaddr_t bkpreg_base(void) 319 { 320 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 321 } 322 323 vaddr_t stm32mp_bkpreg(unsigned int idx) 324 { 325 return bkpreg_base() + (idx * sizeof(uint32_t)); 326 } 327 328 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 329 { 330 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 331 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 332 333 /* Get non-secure mapping address for GPIOZ */ 334 if (bank == GPIO_BANK_Z) 335 return io_pa_or_va_nsec(&gpioz_base); 336 337 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 338 assert(bank <= GPIO_BANK_K); 339 340 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 341 } 342 343 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 344 { 345 if (bank == GPIO_BANK_Z) 346 return 0; 347 348 assert(bank <= GPIO_BANK_K); 349 return bank * GPIO_BANK_OFFSET; 350 } 351 352 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 353 { 354 if (bank == GPIO_BANK_Z) 355 return GPIOZ; 356 357 assert(bank <= GPIO_BANK_K); 358 return GPIOA + bank; 359 } 360