1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32mp1_etzpc.h> 12 #include <drivers/stm32_uart.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/dt.h> 15 #include <kernel/generic_boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 #ifdef CFG_WITH_NSEC_GPIOS 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 31 #endif 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 35 #ifdef CFG_WITH_NSEC_UARTS 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 44 #endif 45 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 57 58 static const struct thread_handlers handlers = { 59 .cpu_on = pm_panic, 60 .cpu_off = pm_panic, 61 .cpu_suspend = pm_panic, 62 .cpu_resume = pm_panic, 63 .system_off = pm_panic, 64 .system_reset = pm_panic, 65 }; 66 67 const struct thread_handlers *generic_boot_get_handlers(void) 68 { 69 return &handlers; 70 } 71 72 #define _ID2STR(id) (#id) 73 #define ID2STR(id) _ID2STR(id) 74 75 static TEE_Result platform_banner(void) 76 { 77 #ifdef CFG_EMBED_DTB 78 IMSG("Platform stm32mp1: flavor %s - DT %s", 79 ID2STR(PLATFORM_FLAVOR), 80 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 81 #else 82 IMSG("Platform stm32mp1: flavor %s - no device tree", 83 ID2STR(PLATFORM_FLAVOR)); 84 #endif 85 86 return TEE_SUCCESS; 87 } 88 service_init(platform_banner); 89 90 /* 91 * Console 92 * 93 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 94 * trace console. Value 0 disables the early console. 95 * 96 * We cannot use the generic serial_console support since probing 97 * the console requires the platform clock driver to be already 98 * up and ready which is done only once service_init are completed. 99 */ 100 static struct stm32_uart_pdata console_data; 101 102 void console_init(void) 103 { 104 /* Early console initialization before MMU setup */ 105 struct uart { 106 paddr_t pa; 107 bool secure; 108 } uarts[] = { 109 [0] = { .pa = 0 }, 110 [1] = { .pa = USART1_BASE, .secure = true, }, 111 [2] = { .pa = USART2_BASE, .secure = false, }, 112 [3] = { .pa = USART3_BASE, .secure = false, }, 113 [4] = { .pa = UART4_BASE, .secure = false, }, 114 [5] = { .pa = UART5_BASE, .secure = false, }, 115 [6] = { .pa = USART6_BASE, .secure = false, }, 116 [7] = { .pa = UART7_BASE, .secure = false, }, 117 [8] = { .pa = UART8_BASE, .secure = false, }, 118 }; 119 120 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 121 assert(!cpu_mmu_enabled()); 122 123 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 124 return; 125 126 /* No clock yet bound to the UART console */ 127 console_data.clock = DT_INFO_INVALID_CLOCK; 128 129 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 130 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 131 132 register_serial_console(&console_data.chip); 133 134 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 135 } 136 137 #ifdef CFG_DT 138 static TEE_Result init_console_from_dt(void) 139 { 140 struct stm32_uart_pdata *pd = NULL; 141 void *fdt = NULL; 142 int node = 0; 143 TEE_Result res = TEE_ERROR_GENERIC; 144 145 fdt = get_embedded_dt(); 146 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 147 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 148 fdt = get_external_dt(); 149 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 150 if (res == TEE_ERROR_ITEM_NOT_FOUND) 151 return TEE_SUCCESS; 152 if (res != TEE_SUCCESS) 153 return res; 154 } 155 156 pd = stm32_uart_init_from_dt_node(fdt, node); 157 if (!pd) { 158 IMSG("DTB disables console"); 159 register_serial_console(NULL); 160 return TEE_SUCCESS; 161 } 162 163 /* Replace early console with the new one */ 164 console_flush(); 165 console_data = *pd; 166 free(pd); 167 register_serial_console(&console_data.chip); 168 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 169 170 return TEE_SUCCESS; 171 } 172 173 /* Probe console from DT once clock inits (service init level) are completed */ 174 service_init_late(init_console_from_dt); 175 #endif 176 177 /* 178 * GIC init, used also for primary/secondary boot core wake completion 179 */ 180 static struct gic_data gic_data; 181 182 void itr_core_handler(void) 183 { 184 gic_it_handle(&gic_data); 185 } 186 187 void main_init_gic(void) 188 { 189 assert(cpu_mmu_enabled()); 190 191 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 192 itr_init(&gic_data.chip); 193 194 stm32mp_register_online_cpu(); 195 } 196 197 void main_secondary_init_gic(void) 198 { 199 gic_cpu_init(&gic_data); 200 201 stm32mp_register_online_cpu(); 202 } 203 204 #ifndef CFG_EMBED_DTB 205 static TEE_Result init_stm32mp1_drivers(void) 206 { 207 /* Without secure DTB support, some drivers must be inited */ 208 stm32_etzpc_init(ETZPC_BASE); 209 210 return TEE_SUCCESS; 211 } 212 driver_init(init_stm32mp1_drivers); 213 #endif /*!CFG_EMBED_DTB*/ 214 215 /* Platform initializations once all drivers are ready */ 216 static TEE_Result init_late_stm32mp1_drivers(void) 217 { 218 /* Secure internal memories for the platform, once ETZPC is ready */ 219 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 220 etzpc_lock_tzma(0); 221 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 222 etzpc_lock_tzma(1); 223 224 /* Static secure DECPROT configuration */ 225 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 226 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 227 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 228 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 229 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 230 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 231 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 232 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 233 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 234 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 235 /* Static non-secure DECPROT configuration */ 236 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 237 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 238 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 239 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 240 /* Release few resource to the non-secure world */ 241 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 242 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 243 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 244 245 return TEE_SUCCESS; 246 } 247 driver_init_late(init_late_stm32mp1_drivers); 248 249 vaddr_t get_gicc_base(void) 250 { 251 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 252 253 return io_pa_or_va_secure(&base); 254 } 255 256 vaddr_t get_gicd_base(void) 257 { 258 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 259 260 return io_pa_or_va_secure(&base); 261 } 262 263 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 264 { 265 cfg->base = BSEC_BASE; 266 cfg->upper_start = STM32MP1_UPPER_OTP_START; 267 cfg->max_id = STM32MP1_OTP_MAX_ID; 268 cfg->closed_device_id = DATA0_OTP; 269 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 270 } 271 272 bool stm32mp_is_closed_device(void) 273 { 274 uint32_t otp = 0; 275 TEE_Result result = TEE_ERROR_GENERIC; 276 277 /* Non closed_device platform expects fuse well programmed to 0 */ 278 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 279 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 280 return false; 281 282 return true; 283 } 284 285 uint32_t may_spin_lock(unsigned int *lock) 286 { 287 if (!lock || !cpu_mmu_enabled()) 288 return 0; 289 290 return cpu_spin_lock_xsave(lock); 291 } 292 293 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 294 { 295 if (!lock || !cpu_mmu_enabled()) 296 return; 297 298 cpu_spin_unlock_xrestore(lock, exceptions); 299 } 300 301 static vaddr_t stm32_tamp_base(void) 302 { 303 static struct io_pa_va base = { .pa = TAMP_BASE }; 304 305 return io_pa_or_va_secure(&base); 306 } 307 308 static vaddr_t bkpreg_base(void) 309 { 310 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 311 } 312 313 vaddr_t stm32mp_bkpreg(unsigned int idx) 314 { 315 return bkpreg_base() + (idx * sizeof(uint32_t)); 316 } 317 318 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 319 { 320 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 321 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 322 323 /* Get non-secure mapping address for GPIOZ */ 324 if (bank == GPIO_BANK_Z) 325 return io_pa_or_va_nsec(&gpioz_base); 326 327 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 328 assert(bank <= GPIO_BANK_K); 329 330 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 331 } 332 333 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 334 { 335 if (bank == GPIO_BANK_Z) 336 return 0; 337 338 assert(bank <= GPIO_BANK_K); 339 return bank * GPIO_BANK_OFFSET; 340 } 341 342 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 343 { 344 if (bank == GPIO_BANK_Z) 345 return GPIOZ; 346 347 assert(bank <= GPIO_BANK_K); 348 return GPIOA + bank; 349 } 350