1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 #ifdef CFG_WITH_NSEC_UARTS 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 40 #endif 41 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 48 49 static void main_fiq(void); 50 51 static const struct thread_handlers handlers = { 52 .std_smc = tee_entry_std, 53 .fast_smc = tee_entry_fast, 54 .nintr = main_fiq, 55 .cpu_on = pm_panic, 56 .cpu_off = pm_panic, 57 .cpu_suspend = pm_panic, 58 .cpu_resume = pm_panic, 59 .system_off = pm_panic, 60 .system_reset = pm_panic, 61 }; 62 63 const struct thread_handlers *generic_boot_get_handlers(void) 64 { 65 return &handlers; 66 } 67 68 #define _ID2STR(id) (#id) 69 #define ID2STR(id) _ID2STR(id) 70 71 static TEE_Result platform_banner(void) 72 { 73 #ifdef CFG_EMBED_DTB 74 IMSG("Platform stm32mp1: flavor %s - DT %s", 75 ID2STR(PLATFORM_FLAVOR), 76 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 77 #else 78 IMSG("Platform stm32mp1: flavor %s - no device tree", 79 ID2STR(PLATFORM_FLAVOR)); 80 #endif 81 82 return TEE_SUCCESS; 83 } 84 service_init(platform_banner); 85 86 /* 87 * Console 88 * 89 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 90 * trace console. Value 0 disables the early console. 91 * 92 * We cannot use the generic serial_console support since probing 93 * the console requires the platform clock driver to be already 94 * up and ready which is done only once service_init are completed. 95 */ 96 static struct stm32_uart_pdata console_data; 97 98 void console_init(void) 99 { 100 /* Early console initialization before MMU setup */ 101 struct uart { 102 uintptr_t pa; 103 bool secure; 104 } uarts[] = { 105 [0] = { .pa = 0 }, 106 [1] = { .pa = USART1_BASE, .secure = true, }, 107 [2] = { .pa = USART2_BASE, .secure = false, }, 108 [3] = { .pa = USART3_BASE, .secure = false, }, 109 [4] = { .pa = UART4_BASE, .secure = false, }, 110 [5] = { .pa = UART5_BASE, .secure = false, }, 111 [6] = { .pa = USART6_BASE, .secure = false, }, 112 [7] = { .pa = UART7_BASE, .secure = false, }, 113 [8] = { .pa = UART8_BASE, .secure = false, }, 114 }; 115 116 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 117 assert(!cpu_mmu_enabled()); 118 119 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 120 return; 121 122 /* No clock yet bound to the UART console */ 123 console_data.clock = DT_INFO_INVALID_CLOCK; 124 125 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 126 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 127 128 register_serial_console(&console_data.chip); 129 130 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 131 } 132 133 #ifdef CFG_DT 134 static TEE_Result init_console_from_dt(void) 135 { 136 struct stm32_uart_pdata *pd; 137 void *fdt; 138 int node; 139 140 if (get_console_node_from_dt(&fdt, &node, NULL, NULL)) 141 return TEE_SUCCESS; 142 143 pd = stm32_uart_init_from_dt_node(fdt, node); 144 if (!pd) { 145 IMSG("DTB disables console"); 146 register_serial_console(NULL); 147 return TEE_SUCCESS; 148 } 149 150 /* Replace early console with the new one */ 151 console_flush(); 152 console_data = *pd; 153 free(pd); 154 register_serial_console(&console_data.chip); 155 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 156 157 return TEE_SUCCESS; 158 } 159 160 /* Probe console from DT once clock inits (service init level) are completed */ 161 service_init_late(init_console_from_dt); 162 #endif 163 164 /* 165 * GIC init, used also for primary/secondary boot core wake completion 166 */ 167 static struct gic_data gic_data; 168 169 static void main_fiq(void) 170 { 171 gic_it_handle(&gic_data); 172 } 173 174 void main_init_gic(void) 175 { 176 assert(cpu_mmu_enabled()); 177 178 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 179 itr_init(&gic_data.chip); 180 181 stm32mp_register_online_cpu(); 182 } 183 184 void main_secondary_init_gic(void) 185 { 186 gic_cpu_init(&gic_data); 187 188 stm32mp_register_online_cpu(); 189 } 190 191 #ifndef CFG_EMBED_DTB 192 static TEE_Result init_stm32mp1_drivers(void) 193 { 194 /* Without secure DTB support, some drivers must be inited */ 195 stm32_etzpc_init(ETZPC_BASE); 196 197 return TEE_SUCCESS; 198 } 199 driver_init(init_stm32mp1_drivers); 200 #endif /*!CFG_EMBED_DTB*/ 201 202 /* Platform initializations once all drivers are ready */ 203 static TEE_Result init_late_stm32mp1_drivers(void) 204 { 205 /* Secure internal memories for the platform, once ETZPC is ready */ 206 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 207 etzpc_lock_tzma(0); 208 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 209 etzpc_lock_tzma(1); 210 211 /* Static secure DECPROT configuration */ 212 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 213 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 214 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 215 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 216 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 217 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 218 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 219 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 220 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 221 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 222 /* Static non-secure DECPROT configuration */ 223 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 224 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 225 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 226 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 227 /* Release few resource to the non-secure world */ 228 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 229 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 230 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 231 232 return TEE_SUCCESS; 233 } 234 driver_init_late(init_late_stm32mp1_drivers); 235 236 uintptr_t get_gicc_base(void) 237 { 238 uintptr_t pbase = GIC_BASE + GICC_OFFSET; 239 240 if (cpu_mmu_enabled()) 241 return (uintptr_t)phys_to_virt_io(pbase); 242 243 return pbase; 244 } 245 246 uintptr_t get_gicd_base(void) 247 { 248 uintptr_t pbase = GIC_BASE + GICD_OFFSET; 249 250 if (cpu_mmu_enabled()) 251 return (uintptr_t)phys_to_virt_io(pbase); 252 253 return pbase; 254 } 255 256 uint32_t may_spin_lock(unsigned int *lock) 257 { 258 if (!lock || !cpu_mmu_enabled()) 259 return 0; 260 261 return cpu_spin_lock_xsave(lock); 262 } 263 264 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 265 { 266 if (!lock || !cpu_mmu_enabled()) 267 return; 268 269 cpu_spin_unlock_xrestore(lock, exceptions); 270 } 271 272 static uintptr_t stm32_tamp_base(void) 273 { 274 static struct io_pa_va base = { .pa = TAMP_BASE }; 275 276 return io_pa_or_va(&base); 277 } 278 279 static uintptr_t bkpreg_base(void) 280 { 281 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 282 } 283 284 uintptr_t stm32mp_bkpreg(unsigned int idx) 285 { 286 return bkpreg_base() + (idx * sizeof(uint32_t)); 287 } 288 289 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 290 { 291 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 292 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 293 294 if (bank == GPIO_BANK_Z) 295 return io_pa_or_va(&gpioz_base); 296 297 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 298 assert(bank <= GPIO_BANK_K); 299 300 return io_pa_or_va(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 301 } 302 303 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 304 { 305 if (bank == GPIO_BANK_Z) 306 return 0; 307 308 assert(bank <= GPIO_BANK_K); 309 return bank * GPIO_BANK_OFFSET; 310 } 311 312 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 313 { 314 if (bank == GPIO_BANK_Z) 315 return GPIOZ; 316 317 assert(bank <= GPIO_BANK_K); 318 return GPIOA + bank; 319 } 320