1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/pm_stubs.h> 21 #include <kernel/spinlock.h> 22 #include <mm/core_memprot.h> 23 #include <platform_config.h> 24 #include <sm/psci.h> 25 #include <stm32_util.h> 26 #include <tee/entry_fast.h> 27 #include <tee/entry_std.h> 28 #include <trace.h> 29 30 #ifdef CFG_WITH_NSEC_GPIOS 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 32 #endif 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 36 #ifdef CFG_WITH_NSEC_UARTS 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 45 #endif 46 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SYSCFG_BASE, SMALL_PAGE_SIZE); 57 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 58 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC_BASE, SMALL_PAGE_SIZE); 59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 60 61 #if DDR_BASE < CFG_TZDRAM_START 62 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 63 #endif 64 65 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 66 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 67 68 #if DRAM_END > TZDRAM_END 69 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 70 #endif 71 72 static const struct thread_handlers handlers = { 73 .cpu_on = pm_panic, 74 .cpu_off = pm_panic, 75 .cpu_suspend = pm_panic, 76 .cpu_resume = pm_panic, 77 .system_off = pm_panic, 78 .system_reset = pm_panic, 79 }; 80 81 const struct thread_handlers *boot_get_handlers(void) 82 { 83 return &handlers; 84 } 85 86 #define _ID2STR(id) (#id) 87 #define ID2STR(id) _ID2STR(id) 88 89 static TEE_Result platform_banner(void) 90 { 91 #ifdef CFG_EMBED_DTB 92 IMSG("Platform stm32mp1: flavor %s - DT %s", 93 ID2STR(PLATFORM_FLAVOR), 94 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 95 #else 96 IMSG("Platform stm32mp1: flavor %s - no device tree", 97 ID2STR(PLATFORM_FLAVOR)); 98 #endif 99 100 return TEE_SUCCESS; 101 } 102 service_init(platform_banner); 103 104 /* 105 * Console 106 * 107 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 108 * trace console. Value 0 disables the early console. 109 * 110 * We cannot use the generic serial_console support since probing 111 * the console requires the platform clock driver to be already 112 * up and ready which is done only once service_init are completed. 113 */ 114 static struct stm32_uart_pdata console_data; 115 116 void console_init(void) 117 { 118 /* Early console initialization before MMU setup */ 119 struct uart { 120 paddr_t pa; 121 bool secure; 122 } uarts[] = { 123 [0] = { .pa = 0 }, 124 [1] = { .pa = USART1_BASE, .secure = true, }, 125 [2] = { .pa = USART2_BASE, .secure = false, }, 126 [3] = { .pa = USART3_BASE, .secure = false, }, 127 [4] = { .pa = UART4_BASE, .secure = false, }, 128 [5] = { .pa = UART5_BASE, .secure = false, }, 129 [6] = { .pa = USART6_BASE, .secure = false, }, 130 [7] = { .pa = UART7_BASE, .secure = false, }, 131 [8] = { .pa = UART8_BASE, .secure = false, }, 132 }; 133 134 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 135 136 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 137 return; 138 139 /* No clock yet bound to the UART console */ 140 console_data.clock = DT_INFO_INVALID_CLOCK; 141 142 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 143 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 144 145 register_serial_console(&console_data.chip); 146 147 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 148 } 149 150 #ifdef CFG_DT 151 static TEE_Result init_console_from_dt(void) 152 { 153 struct stm32_uart_pdata *pd = NULL; 154 void *fdt = NULL; 155 int node = 0; 156 TEE_Result res = TEE_ERROR_GENERIC; 157 158 fdt = get_embedded_dt(); 159 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 160 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 161 fdt = get_external_dt(); 162 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 163 if (res == TEE_ERROR_ITEM_NOT_FOUND) 164 return TEE_SUCCESS; 165 if (res != TEE_SUCCESS) 166 return res; 167 } 168 169 pd = stm32_uart_init_from_dt_node(fdt, node); 170 if (!pd) { 171 IMSG("DTB disables console"); 172 register_serial_console(NULL); 173 return TEE_SUCCESS; 174 } 175 176 /* Replace early console with the new one */ 177 console_flush(); 178 console_data = *pd; 179 free(pd); 180 register_serial_console(&console_data.chip); 181 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 182 183 return TEE_SUCCESS; 184 } 185 186 /* Probe console from DT once clock inits (service init level) are completed */ 187 service_init_late(init_console_from_dt); 188 #endif 189 190 /* 191 * GIC init, used also for primary/secondary boot core wake completion 192 */ 193 static struct gic_data gic_data; 194 195 void itr_core_handler(void) 196 { 197 gic_it_handle(&gic_data); 198 } 199 200 void main_init_gic(void) 201 { 202 assert(cpu_mmu_enabled()); 203 204 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 205 itr_init(&gic_data.chip); 206 207 stm32mp_register_online_cpu(); 208 } 209 210 void main_secondary_init_gic(void) 211 { 212 gic_cpu_init(&gic_data); 213 214 stm32mp_register_online_cpu(); 215 } 216 217 static TEE_Result init_stm32mp1_drivers(void) 218 { 219 /* Without secure DTB support, some drivers must be inited */ 220 if (!IS_ENABLED(CFG_EMBED_DTB)) 221 stm32_etzpc_init(ETZPC_BASE); 222 223 /* Secure internal memories for the platform, once ETZPC is ready */ 224 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 225 etzpc_lock_tzma(0); 226 227 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 228 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 229 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 230 231 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 232 etzpc_lock_tzma(1); 233 234 return TEE_SUCCESS; 235 } 236 service_init_late(init_stm32mp1_drivers); 237 238 vaddr_t get_gicc_base(void) 239 { 240 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 241 242 return io_pa_or_va_secure(&base); 243 } 244 245 vaddr_t get_gicd_base(void) 246 { 247 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 248 249 return io_pa_or_va_secure(&base); 250 } 251 252 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 253 { 254 cfg->base = BSEC_BASE; 255 cfg->upper_start = STM32MP1_UPPER_OTP_START; 256 cfg->max_id = STM32MP1_OTP_MAX_ID; 257 } 258 259 bool stm32mp_is_closed_device(void) 260 { 261 uint32_t otp = 0; 262 TEE_Result result = TEE_ERROR_GENERIC; 263 264 /* Non closed_device platform expects fuse well programmed to 0 */ 265 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 266 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 267 return false; 268 269 return true; 270 } 271 272 bool __weak stm32mp_with_pmic(void) 273 { 274 return false; 275 } 276 277 uint32_t may_spin_lock(unsigned int *lock) 278 { 279 if (!lock || !cpu_mmu_enabled()) 280 return 0; 281 282 return cpu_spin_lock_xsave(lock); 283 } 284 285 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 286 { 287 if (!lock || !cpu_mmu_enabled()) 288 return; 289 290 cpu_spin_unlock_xrestore(lock, exceptions); 291 } 292 293 static vaddr_t stm32_tamp_base(void) 294 { 295 static struct io_pa_va base = { .pa = TAMP_BASE }; 296 297 return io_pa_or_va_secure(&base); 298 } 299 300 static vaddr_t bkpreg_base(void) 301 { 302 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 303 } 304 305 vaddr_t stm32mp_bkpreg(unsigned int idx) 306 { 307 return bkpreg_base() + (idx * sizeof(uint32_t)); 308 } 309 310 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 311 { 312 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 313 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 314 315 /* Get secure mapping address for GPIOZ */ 316 if (bank == GPIO_BANK_Z) 317 return io_pa_or_va_secure(&gpioz_base); 318 319 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 320 assert(bank <= GPIO_BANK_K); 321 322 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 323 } 324 325 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 326 { 327 if (bank == GPIO_BANK_Z) 328 return 0; 329 330 assert(bank <= GPIO_BANK_K); 331 return bank * GPIO_BANK_OFFSET; 332 } 333 334 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 335 { 336 if (bank == GPIO_BANK_Z) 337 return GPIOZ; 338 339 assert(bank <= GPIO_BANK_K); 340 return GPIOA + bank; 341 } 342