1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2022, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_etzpc.h> 13 #include <drivers/stm32_gpio.h> 14 #include <drivers/stm32_iwdg.h> 15 #include <drivers/stm32_tamp.h> 16 #include <drivers/stm32_uart.h> 17 #include <drivers/stm32mp1_etzpc.h> 18 #include <drivers/stm32mp_dt_bindings.h> 19 #include <io.h> 20 #include <kernel/boot.h> 21 #include <kernel/dt.h> 22 #include <kernel/misc.h> 23 #include <kernel/panic.h> 24 #include <kernel/spinlock.h> 25 #include <kernel/tee_misc.h> 26 #include <mm/core_memprot.h> 27 #include <platform_config.h> 28 #include <sm/psci.h> 29 #include <stm32_util.h> 30 #include <string.h> 31 #include <trace.h> 32 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 40 41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB1_BASE, APB1_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB3_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB4_BASE, APB4_SIZE); 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 45 #ifdef CFG_STM32MP13 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB6_BASE, APB6_SIZE); 47 #endif 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 51 52 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 53 54 #define _ID2STR(id) (#id) 55 #define ID2STR(id) _ID2STR(id) 56 57 static TEE_Result platform_banner(void) 58 { 59 IMSG("Platform stm32mp1: flavor %s - DT %s", 60 ID2STR(PLATFORM_FLAVOR), 61 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 62 63 return TEE_SUCCESS; 64 } 65 service_init(platform_banner); 66 67 /* 68 * Console 69 * 70 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 71 * trace console. Value 0 disables the early console. 72 * 73 * We cannot use the generic serial_console support since probing 74 * the console requires the platform clock driver to be already 75 * up and ready which is done only once service_init are completed. 76 */ 77 static struct stm32_uart_pdata console_data; 78 79 void plat_console_init(void) 80 { 81 /* Early console initialization before MMU setup */ 82 struct uart { 83 paddr_t pa; 84 bool secure; 85 } uarts[] = { 86 [0] = { .pa = 0 }, 87 [1] = { .pa = USART1_BASE, .secure = true, }, 88 [2] = { .pa = USART2_BASE, .secure = false, }, 89 [3] = { .pa = USART3_BASE, .secure = false, }, 90 [4] = { .pa = UART4_BASE, .secure = false, }, 91 [5] = { .pa = UART5_BASE, .secure = false, }, 92 [6] = { .pa = USART6_BASE, .secure = false, }, 93 [7] = { .pa = UART7_BASE, .secure = false, }, 94 [8] = { .pa = UART8_BASE, .secure = false, }, 95 }; 96 97 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 98 99 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 100 return; 101 102 /* No clock yet bound to the UART console */ 103 console_data.clock = NULL; 104 105 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 106 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 107 108 register_serial_console(&console_data.chip); 109 110 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 111 } 112 113 static TEE_Result init_console_from_dt(void) 114 { 115 struct stm32_uart_pdata *pd = NULL; 116 void *fdt = NULL; 117 int node = 0; 118 TEE_Result res = TEE_ERROR_GENERIC; 119 120 fdt = get_embedded_dt(); 121 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 122 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 123 fdt = get_external_dt(); 124 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 125 if (res == TEE_ERROR_ITEM_NOT_FOUND) 126 return TEE_SUCCESS; 127 if (res != TEE_SUCCESS) 128 return res; 129 } 130 131 pd = stm32_uart_init_from_dt_node(fdt, node); 132 if (!pd) { 133 IMSG("DTB disables console"); 134 register_serial_console(NULL); 135 return TEE_SUCCESS; 136 } 137 138 /* Replace early console with the new one */ 139 console_flush(); 140 console_data = *pd; 141 register_serial_console(&console_data.chip); 142 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 143 free(pd); 144 145 return TEE_SUCCESS; 146 } 147 148 /* Probe console from DT once clock inits (service init level) are completed */ 149 service_init_late(init_console_from_dt); 150 151 /* 152 * GIC init, used also for primary/secondary boot core wake completion 153 */ 154 void boot_primary_init_intc(void) 155 { 156 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 157 158 stm32mp_register_online_cpu(); 159 } 160 161 void boot_secondary_init_intc(void) 162 { 163 gic_init_per_cpu(); 164 165 stm32mp_register_online_cpu(); 166 } 167 168 #ifdef CFG_STM32MP13 169 #ifdef CFG_STM32_ETZPC 170 /* Configure ETZPC cell and lock it when resource is secure */ 171 static void config_lock_decprot(uint32_t decprot_id, 172 enum etzpc_decprot_attributes decprot_attr) 173 { 174 etzpc_configure_decprot(decprot_id, decprot_attr); 175 176 if (decprot_attr == ETZPC_DECPROT_S_RW) 177 etzpc_lock_decprot(decprot_id); 178 } 179 180 static TEE_Result set_etzpc_secure_configuration(void) 181 { 182 config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 183 config_lock_decprot(STM32MP1_ETZPC_DDRCTRLPHY_ID, 184 ETZPC_DECPROT_NS_R_S_W); 185 186 /* Configure ETZPC with peripheral registering */ 187 config_lock_decprot(STM32MP1_ETZPC_ADC1_ID, ETZPC_DECPROT_NS_RW); 188 config_lock_decprot(STM32MP1_ETZPC_ADC2_ID, ETZPC_DECPROT_NS_RW); 189 config_lock_decprot(STM32MP1_ETZPC_CRYP_ID, ETZPC_DECPROT_NS_RW); 190 config_lock_decprot(STM32MP1_ETZPC_DCMIPP_ID, ETZPC_DECPROT_NS_RW); 191 config_lock_decprot(STM32MP1_ETZPC_ETH1_ID, ETZPC_DECPROT_NS_RW); 192 config_lock_decprot(STM32MP1_ETZPC_ETH2_ID, ETZPC_DECPROT_NS_RW); 193 config_lock_decprot(STM32MP1_ETZPC_FMC_ID, ETZPC_DECPROT_NS_RW); 194 /* HASH is secure */ 195 config_lock_decprot(STM32MP1_ETZPC_HASH_ID, ETZPC_DECPROT_S_RW); 196 config_lock_decprot(STM32MP1_ETZPC_I2C3_ID, ETZPC_DECPROT_NS_RW); 197 /* I2C4 is secure */ 198 config_lock_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_S_RW); 199 config_lock_decprot(STM32MP1_ETZPC_I2C5_ID, ETZPC_DECPROT_NS_RW); 200 /* IWDG1 is secure */ 201 config_lock_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 202 config_lock_decprot(STM32MP1_ETZPC_LPTIM2_ID, ETZPC_DECPROT_NS_RW); 203 /* LPTIM3 is secure */ 204 config_lock_decprot(STM32MP1_ETZPC_LPTIM3_ID, ETZPC_DECPROT_S_RW); 205 config_lock_decprot(STM32MP1_ETZPC_LTDC_ID, ETZPC_DECPROT_NS_RW); 206 /* MCE is secure */ 207 config_lock_decprot(STM32MP1_ETZPC_MCE_ID, ETZPC_DECPROT_S_RW); 208 config_lock_decprot(STM32MP1_ETZPC_OTG_ID, ETZPC_DECPROT_NS_RW); 209 /* PKA is secure */ 210 config_lock_decprot(STM32MP1_ETZPC_PKA_ID, ETZPC_DECPROT_S_RW); 211 config_lock_decprot(STM32MP1_ETZPC_QSPI_ID, ETZPC_DECPROT_NS_RW); 212 /* RNG is secure */ 213 config_lock_decprot(STM32MP1_ETZPC_RNG_ID, ETZPC_DECPROT_S_RW); 214 /* SAES is secure */ 215 config_lock_decprot(STM32MP1_ETZPC_SAES_ID, ETZPC_DECPROT_S_RW); 216 config_lock_decprot(STM32MP1_ETZPC_SDMMC1_ID, ETZPC_DECPROT_NS_RW); 217 config_lock_decprot(STM32MP1_ETZPC_SDMMC2_ID, ETZPC_DECPROT_NS_RW); 218 config_lock_decprot(STM32MP1_ETZPC_SPI4_ID, ETZPC_DECPROT_NS_RW); 219 config_lock_decprot(STM32MP1_ETZPC_SPI5_ID, ETZPC_DECPROT_NS_RW); 220 config_lock_decprot(STM32MP1_ETZPC_SRAM1_ID, ETZPC_DECPROT_NS_RW); 221 config_lock_decprot(STM32MP1_ETZPC_SRAM2_ID, ETZPC_DECPROT_NS_RW); 222 /* SRAM3 is secure */ 223 config_lock_decprot(STM32MP1_ETZPC_SRAM3_ID, ETZPC_DECPROT_S_RW); 224 /* STGENC is secure */ 225 config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 226 /* TIM12 is secure */ 227 config_lock_decprot(STM32MP1_ETZPC_TIM12_ID, ETZPC_DECPROT_S_RW); 228 config_lock_decprot(STM32MP1_ETZPC_TIM13_ID, ETZPC_DECPROT_NS_RW); 229 config_lock_decprot(STM32MP1_ETZPC_TIM14_ID, ETZPC_DECPROT_NS_RW); 230 /* TIM15 is secure */ 231 config_lock_decprot(STM32MP1_ETZPC_TIM15_ID, ETZPC_DECPROT_S_RW); 232 config_lock_decprot(STM32MP1_ETZPC_TIM16_ID, ETZPC_DECPROT_NS_RW); 233 config_lock_decprot(STM32MP1_ETZPC_TIM17_ID, ETZPC_DECPROT_NS_RW); 234 config_lock_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 235 config_lock_decprot(STM32MP1_ETZPC_USART2_ID, ETZPC_DECPROT_NS_RW); 236 config_lock_decprot(STM32MP1_ETZPC_USBPHYCTRL_ID, ETZPC_DECPROT_NS_RW); 237 config_lock_decprot(STM32MP1_ETZPC_VREFBUF_ID, ETZPC_DECPROT_NS_RW); 238 239 return TEE_SUCCESS; 240 } 241 242 driver_init_late(set_etzpc_secure_configuration); 243 #endif /* CFG_STM32_ETZPC */ 244 #endif /* CFG_STM32MP13 */ 245 246 #ifdef CFG_STM32MP15 247 /* 248 * This concerns OP-TEE pager for STM32MP1 to use secure internal 249 * RAMs to execute. TZSRAM refers the TZSRAM_BASE/TZSRAM_SIZE 250 * used in boot.c to locate secure unpaged memory. 251 * 252 * STM32MP15 variants embed 640kB of contiguous securable SRAMs 253 * 254 * +--------------+ <-- SYSRAM_BASE 255 * | | lower part can be assigned to secure world 256 * | SYSRAM 256kB | 4kB granule boundary 257 * | | upper part can be assigned to secure world 258 * +--------------+ <-- SRAM1_BASE (= SYSRAM_BASE + SYSRAM_SIZE) 259 | | full range assigned to non-secure world or 260 * | SRAM1 128kB | to secure world, or to- Cortex-M4 exclusive access 261 * +--------------+ <-- SRAM2_BASE (= SRAM1_BASE + SRAM1_SIZE) 262 | | full range assigned to non-secure world or 263 * | SRAM2 128kB | to secure world, or to- Cortex-M4 exclusive access 264 * +--------------+ <-- SRAM3_BASE (= SRAM2_BASE + SRAM2_SIZE) 265 | | full range assigned to non-secure world or 266 * | SRAM3 64kB | to secure world, or to- Cortex-M4 exclusive access 267 * +--------------+ <-- SRAM4_BASE (= SRAM3_BASE + SRAM3_SIZE) 268 | | full range assigned to non-secure world or 269 * | SRAM4 64kB | to secure world, or to- Cortex-M4 exclusive access 270 * +--------------+ <-- SRAM4_BASE + SRAM4_SIZE 271 * 272 * If SRAMx memories are not used for the companion Cortex-M4 273 * processor, OP-TEE can use this memory. 274 * 275 * SYSRAM configuration for secure/non-secure boundaries requires the 276 * secure SYSRAM memory to start at the SYSRAM physical base address and grow 277 * from there while the non-secure SYSRAM range lies at SYSRAM end addresses 278 * with a 4KB page granule. 279 * 280 * SRAM1, SRAM2, SRAM3 and SRAM4 are independently assigned to secure world, 281 * to non-secure world or possibly to Cortex-M4 exclusive access. Each 282 * assignment covers the full related SRAMx memory range. 283 * 284 * Using non-secure SYSRAM or one of the SRAMx for SCMI message communication 285 * can be done using CFG_STM32MP1_SCMI_SHM_BASE/CFG_STM32MP1_SCMI_SHM_SIZE. 286 * This imposes related memory area is assigned to non-secure world. 287 288 * Using secure internal memories (SYSRAM and/or some SRAMx) with STM32MP15 289 * shall meet this constraints known the TZSRAM physical memory range shall 290 * be contiguous. 291 */ 292 293 #define SYSRAM_END (SYSRAM_BASE + SYSRAM_SIZE) 294 #define SYSRAM_SEC_END (SYSRAM_BASE + SYSRAM_SEC_SIZE) 295 #define SRAMS_END (SRAM4_BASE + SRAM4_SIZE) 296 #define SRAMS_START SRAM1_BASE 297 #define TZSRAM_END (CFG_TZSRAM_START + CFG_TZSRAM_SIZE) 298 299 #define SCMI_SHM_IS_IN_SRAMX ((CFG_STM32MP1_SCMI_SHM_BASE >= SRAM1_BASE) && \ 300 (CFG_STM32MP1_SCMI_SHM_BASE + \ 301 CFG_STM32MP1_SCMI_SHM_SIZE) <= SRAMS_END) 302 303 #define TZSRAM_FITS_IN_SYSRAM_SEC ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 304 (TZSRAM_END <= SYSRAM_SEC_END)) 305 306 #define TZSRAM_FITS_IN_SYSRAM_AND_SRAMS ((CFG_TZSRAM_START >= SYSRAM_BASE) && \ 307 (CFG_TZSRAM_START < SYSRAM_END) && \ 308 (TZSRAM_END > SYSRAM_END) && \ 309 (TZSRAM_END <= SRAMS_END) && \ 310 (SYSRAM_SIZE == SYSRAM_SEC_SIZE)) 311 312 #define TZSRAM_FITS_IN_SRAMS ((CFG_TZSRAM_START >= SRAMS_START) && \ 313 (CFG_TZSRAM_START < SRAMS_END) && \ 314 (TZSRAM_END <= SRAMS_END)) 315 316 #define TZSRAM_IS_IN_DRAM (CFG_TZSRAM_START >= CFG_DRAM_BASE) 317 318 #ifdef CFG_WITH_PAGER 319 /* 320 * At build time, we enforce that, when pager is used, 321 * either TZSRAM fully fits inside SYSRAM secure address range, 322 * or TZSRAM fully fits inside the full SYSRAM and spread inside SRAMx orderly, 323 * or TZSRAM fully fits some inside SRAMs address range, 324 * or TZSRAM is in DDR for debug and test purpose. 325 */ 326 static_assert(TZSRAM_FITS_IN_SYSRAM_SEC || TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || 327 TZSRAM_FITS_IN_SRAMS || TZSRAM_IS_IN_DRAM); 328 #endif 329 330 #if TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || TZSRAM_FITS_IN_SRAMS || \ 331 SCMI_SHM_IS_IN_SRAMX 332 /* At run time we enforce that SRAM1 to SRAM4 are properly assigned if used */ 333 static TEE_Result init_stm32mp15_secure_srams(void) 334 { 335 if (IS_ENABLED(CFG_WITH_PAGER)) { 336 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 337 SRAM1_BASE, SRAM1_SIZE)) 338 stm32mp_register_secure_periph_iomem(SRAM1_BASE); 339 340 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 341 SRAM2_BASE, SRAM2_SIZE)) 342 stm32mp_register_secure_periph_iomem(SRAM2_BASE); 343 344 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 345 SRAM3_BASE, SRAM3_SIZE)) 346 stm32mp_register_secure_periph_iomem(SRAM3_BASE); 347 348 if (core_is_buffer_intersect(CFG_TZSRAM_START, CFG_TZSRAM_SIZE, 349 SRAM4_BASE, SRAM4_SIZE)) 350 stm32mp_register_secure_periph_iomem(SRAM4_BASE); 351 } 352 353 if (SCMI_SHM_IS_IN_SRAMX) { 354 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 355 CFG_STM32MP1_SCMI_SHM_SIZE, 356 SRAM1_BASE, SRAM1_SIZE)) 357 stm32mp_register_non_secure_periph_iomem(SRAM1_BASE); 358 359 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 360 CFG_STM32MP1_SCMI_SHM_SIZE, 361 SRAM2_BASE, SRAM2_SIZE)) 362 stm32mp_register_non_secure_periph_iomem(SRAM2_BASE); 363 364 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 365 CFG_STM32MP1_SCMI_SHM_SIZE, 366 SRAM3_BASE, SRAM3_SIZE)) 367 stm32mp_register_non_secure_periph_iomem(SRAM3_BASE); 368 369 if (core_is_buffer_intersect(CFG_STM32MP1_SCMI_SHM_BASE, 370 CFG_STM32MP1_SCMI_SHM_SIZE, 371 SRAM4_BASE, SRAM4_SIZE)) 372 stm32mp_register_non_secure_periph_iomem(SRAM4_BASE); 373 } 374 375 return TEE_SUCCESS; 376 } 377 378 service_init_late(init_stm32mp15_secure_srams); 379 #endif /* TZSRAM_FITS_IN_SYSRAM_AND_SRAMS || TZSRAM_FITS_IN_SRAMS */ 380 #endif /* CFG_STM32MP15 && CFG_TZSRAM_START */ 381 382 static TEE_Result init_stm32mp1_drivers(void) 383 { 384 /* Secure internal memories for the platform, once ETZPC is ready */ 385 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 386 etzpc_lock_tzma(0); 387 388 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 389 etzpc_lock_tzma(1); 390 391 if (SYSRAM_SIZE > SYSRAM_SEC_SIZE) { 392 size_t nsec_size = SYSRAM_SIZE - SYSRAM_SEC_SIZE; 393 paddr_t nsec_start = SYSRAM_BASE + SYSRAM_SEC_SIZE; 394 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, 395 nsec_size); 396 397 IMSG("Non-secure SYSRAM [%p %p]", va, va + nsec_size - 1); 398 399 /* Clear content from the non-secure part */ 400 memset(va, 0, nsec_size); 401 } 402 403 return TEE_SUCCESS; 404 } 405 406 service_init_late(init_stm32mp1_drivers); 407 408 static TEE_Result init_late_stm32mp1_drivers(void) 409 { 410 TEE_Result res = TEE_ERROR_GENERIC; 411 412 /* Set access permission to TAM backup registers */ 413 if (IS_ENABLED(CFG_STM32_TAMP)) { 414 struct stm32_bkpregs_conf conf = { 415 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 416 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 417 }; 418 419 res = stm32_tamp_set_secure_bkpregs(&conf); 420 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 421 /* TAMP driver was not probed if disabled in the DT */ 422 res = TEE_SUCCESS; 423 } 424 if (res) 425 panic(); 426 } 427 428 return TEE_SUCCESS; 429 } 430 431 driver_init_late(init_late_stm32mp1_drivers); 432 433 vaddr_t stm32_rcc_base(void) 434 { 435 static struct io_pa_va base = { .pa = RCC_BASE }; 436 437 return io_pa_or_va_secure(&base, 1); 438 } 439 440 vaddr_t get_gicd_base(void) 441 { 442 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 443 444 return io_pa_or_va_secure(&base, 1); 445 } 446 447 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 448 { 449 cfg->base = BSEC_BASE; 450 cfg->upper_start = STM32MP1_UPPER_OTP_START; 451 cfg->max_id = STM32MP1_OTP_MAX_ID; 452 } 453 454 bool __weak stm32mp_with_pmic(void) 455 { 456 return false; 457 } 458 459 uint32_t may_spin_lock(unsigned int *lock) 460 { 461 if (!lock || !cpu_mmu_enabled()) 462 return 0; 463 464 return cpu_spin_lock_xsave(lock); 465 } 466 467 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 468 { 469 if (!lock || !cpu_mmu_enabled()) 470 return; 471 472 cpu_spin_unlock_xrestore(lock, exceptions); 473 } 474 475 static vaddr_t stm32_tamp_base(void) 476 { 477 static struct io_pa_va base = { .pa = TAMP_BASE }; 478 479 return io_pa_or_va_secure(&base, 1); 480 } 481 482 static vaddr_t bkpreg_base(void) 483 { 484 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 485 } 486 487 vaddr_t stm32mp_bkpreg(unsigned int idx) 488 { 489 return bkpreg_base() + (idx * sizeof(uint32_t)); 490 } 491 492 static bool __maybe_unused bank_is_valid(unsigned int bank) 493 { 494 if (IS_ENABLED(CFG_STM32MP15)) 495 return bank == GPIO_BANK_Z || bank <= GPIO_BANK_K; 496 497 if (IS_ENABLED(CFG_STM32MP13)) 498 return bank <= GPIO_BANK_I; 499 500 panic(); 501 } 502 503 #ifdef CFG_STM32_IWDG 504 TEE_Result stm32_get_iwdg_otp_config(paddr_t pbase, 505 struct stm32_iwdg_otp_data *otp_data) 506 { 507 unsigned int idx = 0; 508 uint32_t otp_id = 0; 509 size_t bit_len = 0; 510 uint8_t bit_offset = 0; 511 uint32_t otp_value = 0; 512 513 switch (pbase) { 514 case IWDG1_BASE: 515 idx = 0; 516 break; 517 case IWDG2_BASE: 518 idx = 1; 519 break; 520 default: 521 panic(); 522 } 523 524 if (stm32_bsec_find_otp_in_nvmem_layout("hw2_otp", &otp_id, &bit_offset, 525 &bit_len) || 526 bit_len != 32 || bit_offset != 0) 527 panic(); 528 529 if (stm32_bsec_read_otp(&otp_value, otp_id)) 530 panic(); 531 532 otp_data->hw_enabled = otp_value & 533 BIT(idx + HW2_OTP_IWDG_HW_ENABLE_SHIFT); 534 otp_data->disable_on_stop = otp_value & 535 BIT(idx + HW2_OTP_IWDG_FZ_STOP_SHIFT); 536 otp_data->disable_on_standby = otp_value & 537 BIT(idx + HW2_OTP_IWDG_FZ_STANDBY_SHIFT); 538 539 return TEE_SUCCESS; 540 } 541 #endif /*CFG_STM32_IWDG*/ 542 543 #ifdef CFG_STM32_DEBUG_ACCESS 544 static TEE_Result init_debug(void) 545 { 546 TEE_Result res = TEE_SUCCESS; 547 uint32_t conf = stm32_bsec_read_debug_conf(); 548 struct clk *dbg_clk = stm32mp_rcc_clock_id_to_clk(CK_DBG); 549 uint32_t state = 0; 550 551 res = stm32_bsec_get_state(&state); 552 if (res) 553 return res; 554 555 if (state != BSEC_STATE_SEC_CLOSED && conf) { 556 if (IS_ENABLED(CFG_INSECURE)) 557 IMSG("WARNING: All debug accesses are allowed"); 558 559 res = stm32_bsec_write_debug_conf(conf | BSEC_DEBUG_ALL); 560 if (res) 561 return res; 562 563 /* 564 * Enable DBG clock as used to access coprocessor 565 * debug registers 566 */ 567 clk_enable(dbg_clk); 568 } 569 570 return TEE_SUCCESS; 571 } 572 early_init_late(init_debug); 573 #endif /* CFG_STM32_DEBUG_ACCESS */ 574 575 /* Some generic resources need to be unpaged */ 576 DECLARE_KEEP_PAGER(pinctrl_apply_state); 577