1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_uart.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <mm/core_memprot.h> 16 #include <platform_config.h> 17 #include <sm/psci.h> 18 #include <tee/entry_std.h> 19 #include <tee/entry_fast.h> 20 #include <trace.h> 21 22 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CONSOLE_UART_SIZE); 23 24 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 25 register_phys_mem(MEM_AREA_IO_SEC, BKP_REGS_BASE, SMALL_PAGE_SIZE); 26 27 static struct gic_data gic_data; 28 static struct console_pdata console_data; 29 30 static void main_fiq(void) 31 { 32 gic_it_handle(&gic_data); 33 } 34 35 static const struct thread_handlers handlers = { 36 .std_smc = tee_entry_std, 37 .fast_smc = tee_entry_fast, 38 .nintr = main_fiq, 39 .cpu_on = pm_panic, 40 .cpu_off = pm_panic, 41 .cpu_suspend = pm_panic, 42 .cpu_resume = pm_panic, 43 .system_off = pm_panic, 44 .system_reset = pm_panic, 45 }; 46 47 const struct thread_handlers *generic_boot_get_handlers(void) 48 { 49 return &handlers; 50 } 51 52 #define _ID2STR(id) (#id) 53 #define ID2STR(id) _ID2STR(id) 54 55 static TEE_Result platform_banner(void) 56 { 57 #ifdef CFG_EMBED_DTB 58 IMSG("Platform stm32mp1: flavor %s - DT %s", 59 ID2STR(PLATFORM_FLAVOR), 60 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 61 #else 62 IMSG("Platform stm32mp1: flavor %s - no device tree", 63 ID2STR(PLATFORM_FLAVOR)); 64 #endif 65 66 return TEE_SUCCESS; 67 } 68 service_init(platform_banner); 69 70 void console_init(void) 71 { 72 stm32_uart_init(&console_data, CONSOLE_UART_BASE); 73 register_serial_console(&console_data.chip); 74 } 75 76 void main_init_gic(void) 77 { 78 void *gicc_base; 79 void *gicd_base; 80 81 gicc_base = phys_to_virt(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 82 gicd_base = phys_to_virt(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 83 if (!gicc_base || !gicd_base) 84 panic(); 85 86 gic_init(&gic_data, (vaddr_t)gicc_base, (vaddr_t)gicd_base); 87 itr_init(&gic_data.chip); 88 } 89 90 void main_secondary_init_gic(void) 91 { 92 gic_cpu_init(&gic_data); 93 } 94 95 /* 96 * SMP boot support and access to the mailbox 97 */ 98 #define GIC_SEC_SGI_0 8 99 100 static vaddr_t bckreg_base(void) 101 { 102 static void *va; 103 104 if (!cpu_mmu_enabled()) 105 return BKP_REGS_BASE + BKP_REGISTER_OFF; 106 107 if (!va) 108 va = phys_to_virt(BKP_REGS_BASE + BKP_REGISTER_OFF, 109 MEM_AREA_IO_SEC); 110 111 return (vaddr_t)va; 112 } 113 114 static uint32_t *bckreg_address(unsigned int idx) 115 { 116 return (uint32_t *)bckreg_base() + idx; 117 } 118 119 static void release_secondary_early_hpen(size_t pos) 120 { 121 uint32_t *p_entry = bckreg_address(BCKR_CORE1_BRANCH_ADDRESS); 122 uint32_t *p_magic = bckreg_address(BCKR_CORE1_MAGIC_NUMBER); 123 124 *p_entry = TEE_LOAD_ADDR; 125 *p_magic = BOOT_API_A7_CORE1_MAGIC_NUMBER; 126 127 dmb(); 128 isb(); 129 itr_raise_sgi(GIC_SEC_SGI_0, BIT(pos)); 130 } 131 132 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 133 { 134 size_t pos = get_core_pos_mpidr(core_id); 135 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 136 137 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 138 return PSCI_RET_INVALID_PARAMETERS; 139 140 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 141 142 if (core_is_released[pos]) { 143 DMSG("core %zu already released", pos); 144 return PSCI_RET_DENIED; 145 } 146 core_is_released[pos] = true; 147 148 generic_boot_set_core_ns_entry(pos, entry, context_id); 149 release_secondary_early_hpen(pos); 150 151 return PSCI_RET_SUCCESS; 152 } 153