1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55endif 56 57ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 58$(call force,CFG_HWRNG_PTA,n) 59$(call force,CFG_WITH_SOFTWARE_PRNG,y) 60endif 61 62ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 63CFG_STM32MP15_HUK ?= y 64CFG_STM32_HUK_FROM_DT ?= y 65endif 66 67ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 68$(call force,CFG_STM32MP13,y) 69endif 70 71ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 72$(call force,CFG_STM32MP15,y) 73endif 74 75# CFG_STM32MP1x switches are exclusive. 76# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 77# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 78ifeq ($(CFG_STM32MP13),y) 79$(call force,CFG_STM32MP15,n) 80else 81$(call force,CFG_STM32MP15,y) 82$(call force,CFG_STM32MP13,n) 83endif 84ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 85$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 86endif 87ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 88$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 89endif 90 91include core/arch/arm/cpu/cortex-a7.mk 92 93$(call force,CFG_DRIVERS_CLK,y) 94$(call force,CFG_DRIVERS_CLK_DT,y) 95$(call force,CFG_GIC,y) 96$(call force,CFG_INIT_CNTVOFF,y) 97$(call force,CFG_PSCI_ARM32,y) 98$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 99$(call force,CFG_SM_PLATFORM_HANDLER,y) 100$(call force,CFG_STM32_SHARED_IO,y) 101 102ifeq ($(CFG_STM32MP13),y) 103$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 104$(call force,CFG_CORE_RESERVED_SHM,n) 105$(call force,CFG_DRIVERS_CLK_FIXED,y) 106$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 107$(call force,CFG_STM32_GPIO,y) 108$(call force,CFG_STM32MP_CLK_CORE,y) 109$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 110$(call force,CFG_STM32MP13_CLK,y) 111$(call force,CFG_TEE_CORE_NB_CORE,1) 112$(call force,CFG_WITH_NSEC_GPIOS,n) 113CFG_EXTERNAL_DT ?= n 114CFG_STM32MP_OPP_COUNT ?= 2 115CFG_WITH_PAGER ?= n 116endif # CFG_STM32MP13 117 118ifeq ($(CFG_STM32MP15),y) 119$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 120$(call force,CFG_DRIVERS_CLK_FIXED,n) 121$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 122$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 123$(call force,CFG_STM32MP15_CLK,y) 124CFG_CORE_RESERVED_SHM ?= y 125CFG_EXTERNAL_DT ?= y 126CFG_STM32_BSEC_SIP ?= y 127CFG_TEE_CORE_NB_CORE ?= 2 128CFG_WITH_PAGER ?= y 129CFG_WITH_SOFTWARE_PRNG ?= y 130endif # CFG_STM32MP15 131 132ifeq ($(CFG_WITH_PAGER),y) 133CFG_WITH_LPAE ?= n 134endif 135CFG_WITH_LPAE ?= y 136CFG_MMAP_REGIONS ?= 23 137CFG_DTB_MAX_SIZE ?= (256 * 1024) 138CFG_CORE_ASLR ?= n 139 140ifneq ($(CFG_WITH_LPAE),y) 141# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 142CFG_TEE_RAM_VA_SIZE ?= 0x00200000 143endif 144 145ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 146CFG_TZDRAM_START ?= 0xde000000 147CFG_DRAM_SIZE ?= 0x20000000 148endif 149 150CFG_DRAM_BASE ?= 0xc0000000 151CFG_DRAM_SIZE ?= 0x40000000 152CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 153CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 154ifeq ($(CFG_STM32MP15),y) 155CFG_TZDRAM_START ?= 0xfe000000 156ifeq ($(CFG_CORE_RESERVED_SHM),y) 157CFG_TZDRAM_SIZE ?= 0x01e00000 158else 159CFG_TZDRAM_SIZE ?= 0x02000000 160endif 161CFG_TZSRAM_START ?= 0x2ffc0000 162CFG_TZSRAM_SIZE ?= 0x0003f000 163ifeq ($(CFG_CORE_RESERVED_SHM),y) 164CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 165CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 166endif 167else 168CFG_TZDRAM_SIZE ?= 0x02000000 169CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 170endif #CFG_STM32MP15 171 172CFG_STM32_BSEC ?= y 173CFG_STM32_CRYP ?= y 174CFG_STM32_ETZPC ?= y 175CFG_STM32_GPIO ?= y 176CFG_STM32_I2C ?= y 177CFG_STM32_IWDG ?= y 178CFG_STM32_RNG ?= y 179CFG_STM32_RSTCTRL ?= y 180CFG_STM32_TAMP ?= y 181CFG_STM32_UART ?= y 182CFG_STPMIC1 ?= y 183CFG_TZC400 ?= y 184 185CFG_WITH_SOFTWARE_PRNG ?= n 186ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 187$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 188endif 189 190ifeq ($(CFG_STPMIC1),y) 191$(call force,CFG_STM32_I2C,y) 192$(call force,CFG_STM32_GPIO,y) 193endif 194 195# if any crypto driver is enabled, enable the crypto-framework layer 196ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 197$(call force,CFG_STM32_CRYPTO_DRIVER,y) 198endif 199 200CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 201$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 202 203CFG_WDT ?= $(CFG_STM32_IWDG) 204 205# Platform specific configuration 206CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 207 208# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 209ifneq ($(CFG_SCMI_SCPFW),y) 210CFG_SCMI_MSG_DRIVERS ?= y 211endif 212 213# SiP/OEM service for non-secure world 214CFG_STM32_BSEC_SIP ?= n 215CFG_STM32MP1_SCMI_SIP ?= n 216ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 217$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 218$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 219$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 220endif 221 222# Enable BSEC PTA for fuses access management 223CFG_STM32_BSEC_PTA ?= y 224ifeq ($(CFG_STM32_BSEC_PTA),y) 225$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 226endif 227 228# Default enable SCMI PTA support 229CFG_SCMI_PTA ?= y 230ifeq ($(CFG_SCMI_PTA),y) 231ifneq ($(CFG_SCMI_SCPFW),y) 232$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 233$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 234CFG_SCMI_MSG_SHM_MSG ?= y 235CFG_SCMI_MSG_SMT ?= y 236endif # !CFG_SCMI_SCPFW 237endif # CFG_SCMI_PTA 238 239CFG_SCMI_SCPFW ?= n 240ifeq ($(CFG_SCMI_SCPFW),y) 241$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 242endif 243 244CFG_SCMI_MSG_DRIVERS ?= n 245ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 246$(call force,CFG_SCMI_MSG_CLOCK,y) 247$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 248CFG_SCMI_MSG_SHM_MSG ?= y 249CFG_SCMI_MSG_SMT ?= y 250CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 251$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 252endif 253 254ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 255CFG_HWRNG_PTA ?= y 256endif 257ifeq ($(CFG_HWRNG_PTA),y) 258$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 259$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 260$(call force,CFG_HWRNG_QUALITY,1024) 261endif 262 263# Provision enough threads to pass xtest 264ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 265ifeq ($(CFG_WITH_PAGER),y) 266CFG_NUM_THREADS ?= 3 267else 268CFG_NUM_THREADS ?= 10 269endif 270endif 271 272# Default enable some test facitilites 273CFG_ENABLE_EMBEDDED_TESTS ?= y 274CFG_WITH_STATS ?= y 275 276# Enable OTP update with BSEC driver 277CFG_STM32_BSEC_WRITE ?= y 278 279# Default disable some support for pager memory size constraint 280ifeq ($(CFG_WITH_PAGER),y) 281CFG_TEE_CORE_DEBUG ?= n 282CFG_UNWIND ?= n 283CFG_LOCKDEP ?= n 284CFG_TA_BGET_TEST ?= n 285# Default disable early TA compression to support a smaller HEAP size 286CFG_EARLY_TA_COMPRESS ?= n 287CFG_CORE_HEAP_SIZE ?= 49152 288endif 289 290# Non-secure UART and GPIO/pinctrl for the output console 291CFG_WITH_NSEC_GPIOS ?= y 292CFG_WITH_NSEC_UARTS ?= y 293# UART instance used for early console (0 disables early console) 294CFG_STM32_EARLY_CONSOLE_UART ?= 4 295 296# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 297# Disable the HUK by default as it requires a product specific configuration. 298# 299# Configuration must provide OTP indices where HUK is loaded. 300# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 301# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 302# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 303# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 304# 305# Configuration must provide the HUK generation scheme. The following switches 306# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 307# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 308# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 309# content derived with the device UID fuses content. See derivation scheme 310# in stm32mp15_huk.c implementation. 311CFG_STM32MP15_HUK ?= n 312CFG_STM32_HUK_FROM_DT ?= n 313 314ifeq ($(CFG_STM32MP15_HUK),y) 315ifneq ($(CFG_STM32_HUK_FROM_DT),y) 316ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 317$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 318$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 319$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 320$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 321endif 322ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 323$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 324endif 325ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 326$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 327endif 328ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 329$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 330endif 331ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 332$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 333endif 334endif # CFG_STM32_HUK_FROM_DT 335 336CFG_STM32MP15_HUK_BSEC_KEY ?= y 337CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 338ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 339$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 340else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 341$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 342endif 343endif # CFG_STM32MP15_HUK 344 345CFG_TEE_CORE_DEBUG ?= y 346CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 347 348# Sanity on choice config switches 349ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 350$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 351endif 352