1/* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <arm32.h> 29#include <arm32_macros.S> 30#include <arm32_macros_cortex_a9.S> 31#include <asm.S> 32#include <kernel/tz_ssvce_def.h> 33#include <kernel/unwind.h> 34#include <platform_config.h> 35 36.section .text 37.balign 4 38.code 32 39 40/* 41 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 42 * 43 * If PL310 supports FZLW, enable also FZL in A9 core 44 * 45 * Use scratables registers R0-R3. 46 * No stack usage. 47 * LR store return address. 48 * Trap CPU in case of error. 49 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 50 */ 51FUNC arm_cl2_enable , : 52UNWIND( .fnstart) 53 54 /* Enable PL310 ctrl -> only set lsb bit */ 55 mov r1, #0x1 56 str r1, [r0, #PL310_CTRL] 57 58 /* if L2 FLZW enable, enable in L1 */ 59 ldr r1, [r0, #PL310_AUX_CTRL] 60 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 61 read_actlr r0 62 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 63 write_actlr r0 64 65 mov pc, lr 66 67UNWIND( .fnend) 68END_FUNC arm_cl2_enable 69 70/* 71 * Cortex A9 configuration early configuration 72 * 73 * Use scratables registers R0-R3. 74 * No stack usage. 75 * LR store return address. 76 * Trap CPU in case of error. 77 */ 78FUNC plat_cpu_reset_early , : 79UNWIND( .fnstart) 80 81 mov_imm r0, CPU_SCTLR_INIT 82 write_sctlr r0 83 84 mov_imm r0, CPU_ACTLR_INIT 85 write_actlr r0 86 87 mov_imm r0, CPU_NSACR_INIT 88 write_nsacr r0 89 90 mov_imm r0, CPU_PCR_INIT 91 write_pcr r0 92 93 mov pc, lr 94 95UNWIND( .fnend) 96END_FUNC plat_cpu_reset_early 97 98