1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6#include <arm32.h> 7#include <arm32_macros.S> 8#include <arm32_macros_cortex_a9.S> 9#include <asm.S> 10#include <kernel/tz_ssvce_def.h> 11#include <kernel/unwind.h> 12#include <platform_config.h> 13 14.section .text 15.balign 4 16.code 32 17 18/* 19 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 20 * 21 * If PL310 supports FZLW, enable also FZL in A9 core 22 * 23 * Use scratables registers R0-R3. 24 * No stack usage. 25 * LR store return address. 26 * Trap CPU in case of error. 27 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 28 */ 29FUNC arm_cl2_enable , : 30UNWIND( .fnstart) 31 32 /* Enable PL310 ctrl -> only set lsb bit */ 33 mov r1, #0x1 34 str r1, [r0, #PL310_CTRL] 35 36 /* if L2 FLZW enable, enable in L1 */ 37 ldr r1, [r0, #PL310_AUX_CTRL] 38 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 39 read_actlr r0 40 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 41 write_actlr r0 42 43 mov pc, lr 44 45UNWIND( .fnend) 46END_FUNC arm_cl2_enable 47 48/* 49 * Cortex A9 configuration early configuration 50 * 51 * Use scratables registers R0-R3. 52 * No stack usage. 53 * LR store return address. 54 * Trap CPU in case of error. 55 */ 56FUNC plat_cpu_reset_early , : 57UNWIND( .fnstart) 58 59 /* CPSR.A can be modified in any security state. */ 60 mov_imm r0, SCR_AW 61 write_scr r0 62 63 mov_imm r0, CPU_SCTLR_INIT 64 write_sctlr r0 65 66 mov_imm r0, CPU_ACTLR_INIT 67 write_actlr r0 68 69 mov_imm r0, CPU_NSACR_INIT 70 write_nsacr r0 71 72 mov_imm r0, CPU_PCR_INIT 73 write_pcr r0 74 75 mov pc, lr 76 77UNWIND( .fnend) 78END_FUNC plat_cpu_reset_early 79 80