1 /* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm32.h> 29 #include <asc.h> 30 #include <console.h> 31 #include <drivers/gic.h> 32 #include <drivers/pl011.h> 33 #include <io.h> 34 #include <kernel/generic_boot.h> 35 #include <kernel/misc.h> 36 #include <kernel/panic.h> 37 #include <kernel/pm_stubs.h> 38 #include <kernel/tz_ssvce_pl310.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <platform_config.h> 42 #include <stdint.h> 43 #include <tee/entry_std.h> 44 #include <tee/entry_fast.h> 45 #include <trace.h> 46 #include <util.h> 47 48 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CORE_MMU_DEVICE_SIZE); 49 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, CORE_MMU_DEVICE_SIZE); 50 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, CORE_MMU_DEVICE_SIZE); 51 52 static struct gic_data gic_data; 53 static void main_fiq(void); 54 55 #if defined(PLATFORM_FLAVOR_b2260) 56 #define stm_tee_entry_std tee_entry_std 57 static bool ns_resources_ready(void) 58 { 59 return true; 60 } 61 #else 62 /* some nonsecure resource might not be ready (uart) */ 63 static int boot_is_completed __early_bss; 64 static bool ns_resources_ready(void) 65 { 66 return !!boot_is_completed; 67 } 68 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 69 { 70 boot_is_completed = 1; 71 tee_entry_std(smc_args); 72 } 73 #endif 74 75 static const struct thread_handlers handlers = { 76 .std_smc = stm_tee_entry_std, 77 .fast_smc = tee_entry_fast, 78 .fiq = main_fiq, 79 .cpu_on = pm_panic, 80 .cpu_off = pm_panic, 81 .cpu_suspend = pm_panic, 82 .cpu_resume = pm_panic, 83 .system_off = pm_panic, 84 .system_reset = pm_panic, 85 }; 86 87 const struct thread_handlers *generic_boot_get_handlers(void) 88 { 89 return &handlers; 90 } 91 92 static vaddr_t console_base(void) 93 { 94 static void *va __early_bss; 95 96 if (cpu_mmu_enabled()) { 97 if (!va) 98 va = phys_to_virt(UART_CONSOLE_BASE, MEM_AREA_IO_NSEC); 99 return (vaddr_t)va; 100 } 101 return UART_CONSOLE_BASE; 102 } 103 104 void console_init(void) 105 { 106 } 107 108 void console_putc(int ch) 109 { 110 if (ns_resources_ready()) { 111 if (ch == '\n') 112 __asc_xmit_char('\r', console_base()); 113 __asc_xmit_char((char)ch, console_base()); 114 } 115 } 116 117 void console_flush(void) 118 { 119 if (ns_resources_ready()) 120 __asc_flush(console_base()); 121 } 122 123 vaddr_t pl310_base(void) 124 { 125 static void *va __early_bss; 126 127 if (cpu_mmu_enabled()) { 128 if (!va) 129 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 130 return (vaddr_t)va; 131 } 132 return PL310_BASE; 133 } 134 135 void arm_cl2_config(vaddr_t pl310) 136 { 137 /* pl310 off */ 138 write32(0, pl310 + PL310_CTRL); 139 140 /* config PL310 */ 141 write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); 142 write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); 143 write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); 144 write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); 145 write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); 146 147 /* invalidate all pl310 cache ways */ 148 arm_cl2_invbyway(pl310); 149 } 150 151 void plat_cpu_reset_late(void) 152 { 153 int i; 154 155 assert(!cpu_mmu_enabled()); 156 157 /* Allow NSec to Imprecise abort */ 158 write_scr(SCR_AW); 159 160 if (get_core_pos()) 161 return; 162 163 write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); 164 write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); 165 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 166 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 167 write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); 168 169 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 170 write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, 171 pl310_base() + PL310_ADDR_FILT_START); 172 173 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 174 for (i = 0; i < (31 * 4); i += 4) 175 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 176 } 177 178 void main_init_gic(void) 179 { 180 vaddr_t gicc_base; 181 vaddr_t gicd_base; 182 183 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 184 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 185 186 if (!gicc_base || !gicd_base) 187 panic(); 188 189 gic_init(&gic_data, gicc_base, gicd_base); 190 itr_init(&gic_data.chip); 191 } 192 193 void main_secondary_init_gic(void) 194 { 195 gic_cpu_init(&gic_data); 196 } 197 198 static void main_fiq(void) 199 { 200 gic_it_handle(&gic_data); 201 } 202