1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <arm32.h> 30 #include <console.h> 31 #include <drivers/gic.h> 32 #include <drivers/stih_asc.h> 33 #include <io.h> 34 #include <kernel/generic_boot.h> 35 #include <kernel/misc.h> 36 #include <kernel/panic.h> 37 #include <kernel/pm_stubs.h> 38 #include <kernel/tz_ssvce_pl310.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <platform_config.h> 42 #include <stdint.h> 43 #include <tee/entry_std.h> 44 #include <tee/entry_fast.h> 45 #include <trace.h> 46 #include <util.h> 47 48 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 49 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 50 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 51 52 #ifdef DRAM0_BASE 53 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE); 54 #endif 55 #ifdef DRAM1_BASE 56 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE); 57 #endif 58 59 static struct gic_data gic_data; 60 static struct stih_asc_pd console_data; 61 62 static void main_fiq(void); 63 64 #if defined(PLATFORM_FLAVOR_b2260) 65 #define stm_tee_entry_std tee_entry_std 66 static bool ns_resources_ready(void) 67 { 68 return true; 69 } 70 #else 71 /* some nonsecure resource might not be ready (uart) */ 72 static int boot_is_completed; 73 static bool ns_resources_ready(void) 74 { 75 return !!boot_is_completed; 76 } 77 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 78 { 79 boot_is_completed = 1; 80 tee_entry_std(smc_args); 81 } 82 #endif 83 84 static const struct thread_handlers handlers = { 85 .std_smc = stm_tee_entry_std, 86 .fast_smc = tee_entry_fast, 87 .nintr = main_fiq, 88 .cpu_on = pm_panic, 89 .cpu_off = pm_panic, 90 .cpu_suspend = pm_panic, 91 .cpu_resume = pm_panic, 92 .system_off = pm_panic, 93 .system_reset = pm_panic, 94 }; 95 96 const struct thread_handlers *generic_boot_get_handlers(void) 97 { 98 return &handlers; 99 } 100 101 void console_init(void) 102 { 103 stih_asc_init(&console_data, UART_CONSOLE_BASE); 104 } 105 106 void console_putc(int ch) 107 { 108 109 if (ns_resources_ready()) { 110 struct serial_chip *cons = &console_data.chip; 111 112 if (ch == '\n') 113 cons->ops->putc(cons, '\r'); 114 cons->ops->putc(cons, ch); 115 } 116 } 117 118 void console_flush(void) 119 { 120 if (ns_resources_ready()) { 121 struct serial_chip *cons = &console_data.chip; 122 123 cons->ops->flush(cons); 124 } 125 } 126 127 vaddr_t pl310_base(void) 128 { 129 static void *va; 130 131 if (cpu_mmu_enabled()) { 132 if (!va) 133 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 134 return (vaddr_t)va; 135 } 136 return PL310_BASE; 137 } 138 139 void arm_cl2_config(vaddr_t pl310) 140 { 141 /* pl310 off */ 142 write32(0, pl310 + PL310_CTRL); 143 144 /* config PL310 */ 145 write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); 146 write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); 147 write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); 148 write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); 149 write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); 150 151 /* invalidate all pl310 cache ways */ 152 arm_cl2_invbyway(pl310); 153 } 154 155 void plat_cpu_reset_late(void) 156 { 157 int i; 158 159 assert(!cpu_mmu_enabled()); 160 161 /* Allow NSec to Imprecise abort */ 162 write_scr(SCR_AW); 163 164 if (get_core_pos()) 165 return; 166 167 write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); 168 write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); 169 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 170 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 171 write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); 172 173 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 174 write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, 175 pl310_base() + PL310_ADDR_FILT_START); 176 177 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 178 for (i = 0; i < (31 * 4); i += 4) 179 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 180 } 181 182 void main_init_gic(void) 183 { 184 vaddr_t gicc_base; 185 vaddr_t gicd_base; 186 187 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 188 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 189 190 if (!gicc_base || !gicd_base) 191 panic(); 192 193 gic_init(&gic_data, gicc_base, gicd_base); 194 itr_init(&gic_data.chip); 195 } 196 197 void main_secondary_init_gic(void) 198 { 199 gic_cpu_init(&gic_data); 200 } 201 202 static void main_fiq(void) 203 { 204 gic_it_handle(&gic_data); 205 } 206