1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6 #include <arm32.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/stih_asc.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 #include <kernel/tz_ssvce_pl310.h> 16 #include <mm/core_memprot.h> 17 #include <mm/core_mmu.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <tee/entry_fast.h> 21 #include <tee/entry_std.h> 22 #include <trace.h> 23 #include <util.h> 24 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 28 29 #ifdef DRAM0_BASE 30 register_ddr(DRAM0_BASE, DRAM0_SIZE); 31 #endif 32 #ifdef DRAM1_BASE 33 register_ddr(DRAM1_BASE, DRAM1_SIZE); 34 #endif 35 36 static struct gic_data gic_data; 37 static struct stih_asc_pd console_data; 38 39 #if defined(PLATFORM_FLAVOR_b2260) 40 static bool ns_resources_ready(void) 41 { 42 return true; 43 } 44 #else 45 /* some nonsecure resource might not be ready (uart) */ 46 static int boot_is_completed; 47 static bool ns_resources_ready(void) 48 { 49 return !!boot_is_completed; 50 } 51 52 /* Overriding the default __weak tee_entry_std() */ 53 TEE_Result tee_entry_std(struct optee_msg_arg *arg, uint32_t num_params) 54 { 55 boot_is_completed = 1; 56 57 return __tee_entry_std(arg, num_params); 58 } 59 #endif 60 61 void console_init(void) 62 { 63 stih_asc_init(&console_data, UART_CONSOLE_BASE); 64 } 65 66 void console_putc(int ch) 67 { 68 69 if (ns_resources_ready()) { 70 struct serial_chip *cons = &console_data.chip; 71 72 if (ch == '\n') 73 cons->ops->putc(cons, '\r'); 74 cons->ops->putc(cons, ch); 75 } 76 } 77 78 void console_flush(void) 79 { 80 if (ns_resources_ready()) { 81 struct serial_chip *cons = &console_data.chip; 82 83 cons->ops->flush(cons); 84 } 85 } 86 87 vaddr_t pl310_base(void) 88 { 89 static void *va; 90 91 if (cpu_mmu_enabled()) { 92 if (!va) 93 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); 94 return (vaddr_t)va; 95 } 96 return PL310_BASE; 97 } 98 99 void arm_cl2_config(vaddr_t pl310) 100 { 101 /* pl310 off */ 102 io_write32(pl310 + PL310_CTRL, 0); 103 104 /* config PL310 */ 105 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 106 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 107 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 108 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 109 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 110 111 /* invalidate all pl310 cache ways */ 112 arm_cl2_invbyway(pl310); 113 } 114 115 void plat_primary_init_early(void) 116 { 117 int i; 118 119 assert(!cpu_mmu_enabled()); 120 121 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); 122 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); 123 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); 124 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); 125 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); 126 127 io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); 128 io_write32(pl310_base() + PL310_ADDR_FILT_START, 129 CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); 130 131 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 132 for (i = 0; i < (31 * 4); i += 4) 133 io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); 134 } 135 136 void main_init_gic(void) 137 { 138 gic_init(&gic_data, GIC_CPU_BASE, GIC_DIST_BASE); 139 itr_init(&gic_data.chip); 140 } 141 142 void main_secondary_init_gic(void) 143 { 144 gic_cpu_init(&gic_data); 145 } 146 147 void itr_core_handler(void) 148 { 149 gic_it_handle(&gic_data); 150 } 151