1 /* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm32.h> 29 #include <console.h> 30 #include <drivers/gic.h> 31 #include <drivers/stih_asc.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/misc.h> 35 #include <kernel/panic.h> 36 #include <kernel/pm_stubs.h> 37 #include <kernel/tz_ssvce_pl310.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 #include <tee/entry_std.h> 43 #include <tee/entry_fast.h> 44 #include <trace.h> 45 #include <util.h> 46 47 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 48 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 49 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 50 51 static struct gic_data gic_data; 52 static struct stih_asc_pd console_data; 53 54 static void main_fiq(void); 55 56 #if defined(PLATFORM_FLAVOR_b2260) 57 #define stm_tee_entry_std tee_entry_std 58 static bool ns_resources_ready(void) 59 { 60 return true; 61 } 62 #else 63 /* some nonsecure resource might not be ready (uart) */ 64 static int boot_is_completed; 65 static bool ns_resources_ready(void) 66 { 67 return !!boot_is_completed; 68 } 69 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 70 { 71 boot_is_completed = 1; 72 tee_entry_std(smc_args); 73 } 74 #endif 75 76 static const struct thread_handlers handlers = { 77 .std_smc = stm_tee_entry_std, 78 .fast_smc = tee_entry_fast, 79 .nintr = main_fiq, 80 .cpu_on = pm_panic, 81 .cpu_off = pm_panic, 82 .cpu_suspend = pm_panic, 83 .cpu_resume = pm_panic, 84 .system_off = pm_panic, 85 .system_reset = pm_panic, 86 }; 87 88 const struct thread_handlers *generic_boot_get_handlers(void) 89 { 90 return &handlers; 91 } 92 93 void console_init(void) 94 { 95 stih_asc_init(&console_data, UART_CONSOLE_BASE); 96 } 97 98 void console_putc(int ch) 99 { 100 101 if (ns_resources_ready()) { 102 struct serial_chip *cons = &console_data.chip; 103 104 if (ch == '\n') 105 cons->ops->putc(cons, '\r'); 106 cons->ops->putc(cons, ch); 107 } 108 } 109 110 void console_flush(void) 111 { 112 if (ns_resources_ready()) { 113 struct serial_chip *cons = &console_data.chip; 114 115 cons->ops->flush(cons); 116 } 117 } 118 119 vaddr_t pl310_base(void) 120 { 121 static void *va; 122 123 if (cpu_mmu_enabled()) { 124 if (!va) 125 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 126 return (vaddr_t)va; 127 } 128 return PL310_BASE; 129 } 130 131 void arm_cl2_config(vaddr_t pl310) 132 { 133 /* pl310 off */ 134 write32(0, pl310 + PL310_CTRL); 135 136 /* config PL310 */ 137 write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); 138 write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); 139 write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); 140 write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); 141 write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); 142 143 /* invalidate all pl310 cache ways */ 144 arm_cl2_invbyway(pl310); 145 } 146 147 void plat_cpu_reset_late(void) 148 { 149 int i; 150 151 assert(!cpu_mmu_enabled()); 152 153 /* Allow NSec to Imprecise abort */ 154 write_scr(SCR_AW); 155 156 if (get_core_pos()) 157 return; 158 159 write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); 160 write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); 161 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 162 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 163 write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); 164 165 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 166 write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, 167 pl310_base() + PL310_ADDR_FILT_START); 168 169 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 170 for (i = 0; i < (31 * 4); i += 4) 171 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 172 } 173 174 void main_init_gic(void) 175 { 176 vaddr_t gicc_base; 177 vaddr_t gicd_base; 178 179 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 180 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 181 182 if (!gicc_base || !gicd_base) 183 panic(); 184 185 gic_init(&gic_data, gicc_base, gicd_base); 186 itr_init(&gic_data.chip); 187 } 188 189 void main_secondary_init_gic(void) 190 { 191 gic_cpu_init(&gic_data); 192 } 193 194 static void main_fiq(void) 195 { 196 gic_it_handle(&gic_data); 197 } 198