1 /* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm32.h> 29 #include <console.h> 30 #include <drivers/gic.h> 31 #include <drivers/stih_asc.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/misc.h> 35 #include <kernel/panic.h> 36 #include <kernel/pm_stubs.h> 37 #include <kernel/tz_ssvce_pl310.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 #include <tee/entry_std.h> 43 #include <tee/entry_fast.h> 44 #include <trace.h> 45 #include <util.h> 46 47 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 48 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 49 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 50 51 #ifdef DRAM0_BASE 52 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE); 53 #endif 54 #ifdef DRAM1_BASE 55 register_nsec_ddr(DRAM1_BASE, DRAM1_SIZE); 56 #endif 57 58 static struct gic_data gic_data; 59 static struct stih_asc_pd console_data; 60 61 static void main_fiq(void); 62 63 #if defined(PLATFORM_FLAVOR_b2260) 64 #define stm_tee_entry_std tee_entry_std 65 static bool ns_resources_ready(void) 66 { 67 return true; 68 } 69 #else 70 /* some nonsecure resource might not be ready (uart) */ 71 static int boot_is_completed; 72 static bool ns_resources_ready(void) 73 { 74 return !!boot_is_completed; 75 } 76 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 77 { 78 boot_is_completed = 1; 79 tee_entry_std(smc_args); 80 } 81 #endif 82 83 static const struct thread_handlers handlers = { 84 .std_smc = stm_tee_entry_std, 85 .fast_smc = tee_entry_fast, 86 .nintr = main_fiq, 87 .cpu_on = pm_panic, 88 .cpu_off = pm_panic, 89 .cpu_suspend = pm_panic, 90 .cpu_resume = pm_panic, 91 .system_off = pm_panic, 92 .system_reset = pm_panic, 93 }; 94 95 const struct thread_handlers *generic_boot_get_handlers(void) 96 { 97 return &handlers; 98 } 99 100 void console_init(void) 101 { 102 stih_asc_init(&console_data, UART_CONSOLE_BASE); 103 } 104 105 void console_putc(int ch) 106 { 107 108 if (ns_resources_ready()) { 109 struct serial_chip *cons = &console_data.chip; 110 111 if (ch == '\n') 112 cons->ops->putc(cons, '\r'); 113 cons->ops->putc(cons, ch); 114 } 115 } 116 117 void console_flush(void) 118 { 119 if (ns_resources_ready()) { 120 struct serial_chip *cons = &console_data.chip; 121 122 cons->ops->flush(cons); 123 } 124 } 125 126 vaddr_t pl310_base(void) 127 { 128 static void *va; 129 130 if (cpu_mmu_enabled()) { 131 if (!va) 132 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 133 return (vaddr_t)va; 134 } 135 return PL310_BASE; 136 } 137 138 void arm_cl2_config(vaddr_t pl310) 139 { 140 /* pl310 off */ 141 write32(0, pl310 + PL310_CTRL); 142 143 /* config PL310 */ 144 write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); 145 write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); 146 write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); 147 write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); 148 write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); 149 150 /* invalidate all pl310 cache ways */ 151 arm_cl2_invbyway(pl310); 152 } 153 154 void plat_cpu_reset_late(void) 155 { 156 int i; 157 158 assert(!cpu_mmu_enabled()); 159 160 /* Allow NSec to Imprecise abort */ 161 write_scr(SCR_AW); 162 163 if (get_core_pos()) 164 return; 165 166 write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); 167 write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); 168 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 169 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 170 write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); 171 172 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 173 write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, 174 pl310_base() + PL310_ADDR_FILT_START); 175 176 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 177 for (i = 0; i < (31 * 4); i += 4) 178 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 179 } 180 181 void main_init_gic(void) 182 { 183 vaddr_t gicc_base; 184 vaddr_t gicd_base; 185 186 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 187 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 188 189 if (!gicc_base || !gicd_base) 190 panic(); 191 192 gic_init(&gic_data, gicc_base, gicd_base); 193 itr_init(&gic_data.chip); 194 } 195 196 void main_secondary_init_gic(void) 197 { 198 gic_cpu_init(&gic_data); 199 } 200 201 static void main_fiq(void) 202 { 203 gic_it_handle(&gic_data); 204 } 205