1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6 #include <arm32.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/stih_asc.h> 10 #include <io.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 #include <kernel/pm_stubs.h> 16 #include <kernel/tz_ssvce_pl310.h> 17 #include <mm/core_memprot.h> 18 #include <mm/core_mmu.h> 19 #include <platform_config.h> 20 #include <stdint.h> 21 #include <tee/entry_fast.h> 22 #include <tee/entry_std.h> 23 #include <trace.h> 24 #include <util.h> 25 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 28 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 29 30 #ifdef DRAM0_BASE 31 register_ddr(DRAM0_BASE, DRAM0_SIZE); 32 #endif 33 #ifdef DRAM1_BASE 34 register_ddr(DRAM1_BASE, DRAM1_SIZE); 35 #endif 36 37 static struct gic_data gic_data; 38 static struct stih_asc_pd console_data; 39 40 #if defined(PLATFORM_FLAVOR_b2260) 41 static bool ns_resources_ready(void) 42 { 43 return true; 44 } 45 #else 46 /* some nonsecure resource might not be ready (uart) */ 47 static int boot_is_completed; 48 static bool ns_resources_ready(void) 49 { 50 return !!boot_is_completed; 51 } 52 53 /* Overriding the default __weak tee_entry_std() */ 54 uint32_t tee_entry_std(struct optee_msg_arg *arg, uint32_t num_params) 55 { 56 boot_is_completed = 1; 57 58 return __tee_entry_std(arg, num_params); 59 } 60 #endif 61 62 static const struct thread_handlers handlers = { 63 .cpu_on = pm_panic, 64 .cpu_off = pm_panic, 65 .cpu_suspend = pm_panic, 66 .cpu_resume = pm_panic, 67 .system_off = pm_panic, 68 .system_reset = pm_panic, 69 }; 70 71 const struct thread_handlers *generic_boot_get_handlers(void) 72 { 73 return &handlers; 74 } 75 76 void console_init(void) 77 { 78 stih_asc_init(&console_data, UART_CONSOLE_BASE); 79 } 80 81 void console_putc(int ch) 82 { 83 84 if (ns_resources_ready()) { 85 struct serial_chip *cons = &console_data.chip; 86 87 if (ch == '\n') 88 cons->ops->putc(cons, '\r'); 89 cons->ops->putc(cons, ch); 90 } 91 } 92 93 void console_flush(void) 94 { 95 if (ns_resources_ready()) { 96 struct serial_chip *cons = &console_data.chip; 97 98 cons->ops->flush(cons); 99 } 100 } 101 102 vaddr_t pl310_base(void) 103 { 104 static void *va; 105 106 if (cpu_mmu_enabled()) { 107 if (!va) 108 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 109 return (vaddr_t)va; 110 } 111 return PL310_BASE; 112 } 113 114 void arm_cl2_config(vaddr_t pl310) 115 { 116 /* pl310 off */ 117 io_write32(pl310 + PL310_CTRL, 0); 118 119 /* config PL310 */ 120 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 121 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 122 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 123 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 124 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 125 126 /* invalidate all pl310 cache ways */ 127 arm_cl2_invbyway(pl310); 128 } 129 130 void plat_cpu_reset_late(void) 131 { 132 int i; 133 134 assert(!cpu_mmu_enabled()); 135 136 /* Allow NSec to Imprecise abort */ 137 write_scr(SCR_AW); 138 139 if (get_core_pos()) 140 return; 141 142 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); 143 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); 144 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); 145 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); 146 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); 147 148 io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); 149 io_write32(pl310_base() + PL310_ADDR_FILT_START, 150 CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); 151 152 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 153 for (i = 0; i < (31 * 4); i += 4) 154 io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); 155 } 156 157 void main_init_gic(void) 158 { 159 vaddr_t gicc_base; 160 vaddr_t gicd_base; 161 162 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 163 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 164 165 if (!gicc_base || !gicd_base) 166 panic(); 167 168 gic_init(&gic_data, gicc_base, gicd_base); 169 itr_init(&gic_data.chip); 170 } 171 172 void main_secondary_init_gic(void) 173 { 174 gic_cpu_init(&gic_data); 175 } 176 177 void itr_core_handler(void) 178 { 179 gic_it_handle(&gic_data); 180 } 181