1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6 #include <arm32.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/stih_asc.h> 10 #include <io.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <kernel/tz_ssvce_pl310.h> 16 #include <mm/core_mmu.h> 17 #include <mm/core_memprot.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <tee/entry_std.h> 21 #include <tee/entry_fast.h> 22 #include <trace.h> 23 #include <util.h> 24 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 28 29 #ifdef DRAM0_BASE 30 register_ddr(DRAM0_BASE, DRAM0_SIZE); 31 #endif 32 #ifdef DRAM1_BASE 33 register_ddr(DRAM1_BASE, DRAM1_SIZE); 34 #endif 35 36 static struct gic_data gic_data; 37 static struct stih_asc_pd console_data; 38 39 static void main_fiq(void); 40 41 #if defined(PLATFORM_FLAVOR_b2260) 42 #define stm_tee_entry_std tee_entry_std 43 static bool ns_resources_ready(void) 44 { 45 return true; 46 } 47 #else 48 /* some nonsecure resource might not be ready (uart) */ 49 static int boot_is_completed; 50 static bool ns_resources_ready(void) 51 { 52 return !!boot_is_completed; 53 } 54 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 55 { 56 boot_is_completed = 1; 57 tee_entry_std(smc_args); 58 } 59 #endif 60 61 static const struct thread_handlers handlers = { 62 .std_smc = stm_tee_entry_std, 63 .fast_smc = tee_entry_fast, 64 .nintr = main_fiq, 65 .cpu_on = pm_panic, 66 .cpu_off = pm_panic, 67 .cpu_suspend = pm_panic, 68 .cpu_resume = pm_panic, 69 .system_off = pm_panic, 70 .system_reset = pm_panic, 71 }; 72 73 const struct thread_handlers *generic_boot_get_handlers(void) 74 { 75 return &handlers; 76 } 77 78 void console_init(void) 79 { 80 stih_asc_init(&console_data, UART_CONSOLE_BASE); 81 } 82 83 void console_putc(int ch) 84 { 85 86 if (ns_resources_ready()) { 87 struct serial_chip *cons = &console_data.chip; 88 89 if (ch == '\n') 90 cons->ops->putc(cons, '\r'); 91 cons->ops->putc(cons, ch); 92 } 93 } 94 95 void console_flush(void) 96 { 97 if (ns_resources_ready()) { 98 struct serial_chip *cons = &console_data.chip; 99 100 cons->ops->flush(cons); 101 } 102 } 103 104 vaddr_t pl310_base(void) 105 { 106 static void *va; 107 108 if (cpu_mmu_enabled()) { 109 if (!va) 110 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 111 return (vaddr_t)va; 112 } 113 return PL310_BASE; 114 } 115 116 void arm_cl2_config(vaddr_t pl310) 117 { 118 /* pl310 off */ 119 io_write32(pl310 + PL310_CTRL, 0); 120 121 /* config PL310 */ 122 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 123 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 124 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 125 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 126 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 127 128 /* invalidate all pl310 cache ways */ 129 arm_cl2_invbyway(pl310); 130 } 131 132 void plat_cpu_reset_late(void) 133 { 134 int i; 135 136 assert(!cpu_mmu_enabled()); 137 138 /* Allow NSec to Imprecise abort */ 139 write_scr(SCR_AW); 140 141 if (get_core_pos()) 142 return; 143 144 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); 145 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); 146 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); 147 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); 148 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); 149 150 io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); 151 io_write32(pl310_base() + PL310_ADDR_FILT_START, 152 CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); 153 154 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 155 for (i = 0; i < (31 * 4); i += 4) 156 io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); 157 } 158 159 void main_init_gic(void) 160 { 161 vaddr_t gicc_base; 162 vaddr_t gicd_base; 163 164 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 165 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 166 167 if (!gicc_base || !gicd_base) 168 panic(); 169 170 gic_init(&gic_data, gicc_base, gicd_base); 171 itr_init(&gic_data.chip); 172 } 173 174 void main_secondary_init_gic(void) 175 { 176 gic_cpu_init(&gic_data); 177 } 178 179 static void main_fiq(void) 180 { 181 gic_it_handle(&gic_data); 182 } 183