1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6 #include <arm32.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/stih_asc.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/tz_ssvce_pl310.h> 15 #include <mm/core_memprot.h> 16 #include <mm/core_mmu.h> 17 #include <platform_config.h> 18 #include <stdint.h> 19 #include <tee/entry_fast.h> 20 #include <tee/entry_std.h> 21 #include <trace.h> 22 #include <util.h> 23 24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 26 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 27 28 #ifdef DRAM0_BASE 29 register_ddr(DRAM0_BASE, DRAM0_SIZE); 30 #endif 31 #ifdef DRAM1_BASE 32 register_ddr(DRAM1_BASE, DRAM1_SIZE); 33 #endif 34 35 static struct stih_asc_pd console_data; 36 37 #if defined(PLATFORM_FLAVOR_b2260) 38 static bool ns_resources_ready(void) 39 { 40 return true; 41 } 42 #else 43 /* some nonsecure resource might not be ready (uart) */ 44 static int boot_is_completed; 45 static bool ns_resources_ready(void) 46 { 47 return !!boot_is_completed; 48 } 49 50 /* Overriding the default __weak tee_entry_std() */ 51 TEE_Result tee_entry_std(struct optee_msg_arg *arg, uint32_t num_params) 52 { 53 boot_is_completed = 1; 54 55 return __tee_entry_std(arg, num_params); 56 } 57 #endif 58 59 void plat_console_init(void) 60 { 61 stih_asc_init(&console_data, UART_CONSOLE_BASE); 62 } 63 64 void console_putc(int ch) 65 { 66 67 if (ns_resources_ready()) { 68 struct serial_chip *cons = &console_data.chip; 69 70 if (ch == '\n') 71 cons->ops->putc(cons, '\r'); 72 cons->ops->putc(cons, ch); 73 } 74 } 75 76 void console_flush(void) 77 { 78 if (ns_resources_ready()) { 79 struct serial_chip *cons = &console_data.chip; 80 81 if (cons->ops->flush) 82 cons->ops->flush(cons); 83 } 84 } 85 86 vaddr_t pl310_base(void) 87 { 88 static void *va; 89 90 if (cpu_mmu_enabled()) { 91 if (!va) 92 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); 93 return (vaddr_t)va; 94 } 95 return PL310_BASE; 96 } 97 98 void arm_cl2_config(vaddr_t pl310) 99 { 100 /* pl310 off */ 101 io_write32(pl310 + PL310_CTRL, 0); 102 103 /* config PL310 */ 104 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 105 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 106 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 107 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 108 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 109 110 /* invalidate all pl310 cache ways */ 111 arm_cl2_invbyway(pl310); 112 } 113 114 void plat_primary_init_early(void) 115 { 116 int i; 117 118 assert(!cpu_mmu_enabled()); 119 120 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); 121 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); 122 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); 123 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); 124 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); 125 126 io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); 127 io_write32(pl310_base() + PL310_ADDR_FILT_START, 128 CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); 129 130 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 131 for (i = 0; i < (31 * 4); i += 4) 132 io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); 133 } 134 135 void boot_primary_init_intc(void) 136 { 137 gic_init(GIC_CPU_BASE, GIC_DIST_BASE); 138 } 139 140 void boot_secondary_init_intc(void) 141 { 142 gic_init_per_cpu(); 143 } 144