xref: /optee_os/core/arch/arm/plat-sprd/main.c (revision 5b25c76ac40f830867e3d60800120ffd7874e8dc)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2016, Spreadtrum Communications Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  * this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  * this list of conditions and the following disclaimer in the documentation
14  * and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <drivers/gic.h>
30 #include <kernel/generic_boot.h>
31 #include <kernel/interrupt.h>
32 #include <kernel/panic.h>
33 #include <kernel/pm_stubs.h>
34 #include <mm/core_memprot.h>
35 #include <platform_config.h>
36 #include <tee/entry_fast.h>
37 #include <tee/entry_std.h>
38 #include <trace.h>
39 
40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
41 			ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
42 			CORE_MMU_PGDIR_SIZE);
43 
44 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
45 			ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
46 			CORE_MMU_PGDIR_SIZE);
47 
48 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
49 			ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
50 			CORE_MMU_PGDIR_SIZE);
51 
52 static const struct thread_handlers handlers = {
53 	.cpu_on = cpu_on_handler,
54 	.cpu_off = pm_do_nothing,
55 	.cpu_suspend = pm_do_nothing,
56 	.cpu_resume = pm_do_nothing,
57 	.system_off = pm_do_nothing,
58 	.system_reset = pm_do_nothing,
59 };
60 
61 static struct gic_data gic_data;
62 
63 const struct thread_handlers *generic_boot_get_handlers(void)
64 {
65 	return &handlers;
66 }
67 
68 void main_init_gic(void)
69 {
70 	vaddr_t gicc_base;
71 	vaddr_t gicd_base;
72 
73 	gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
74 					  MEM_AREA_IO_SEC);
75 	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
76 					  MEM_AREA_IO_SEC);
77 	if (!gicc_base || !gicd_base)
78 		panic();
79 
80 	gic_init_base_addr(&gic_data, gicc_base, gicd_base);
81 
82 	itr_init(&gic_data.chip);
83 }
84 
85 void itr_core_handler(void)
86 {
87 	gic_it_handle(&gic_data);
88 }
89