1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 * Copyright (c) 2021, Microchip 5 */ 6 7 #include <at91_clk.h> 8 #include <confine_array_index.h> 9 #include <drivers/atmel_rstc.h> 10 #include <drivers/rstctrl.h> 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <dt-bindings/clock/at91.h> 14 #include <initcall.h> 15 #include <tee_api_defines.h> 16 17 static_assert(SMT_BUF_SLOT_SIZE <= CFG_SCMI_SHMEM_SIZE); 18 19 register_phys_mem(MEM_AREA_IO_NSEC, CFG_SCMI_SHMEM_START, CFG_SCMI_SHMEM_SIZE); 20 21 #define RESET_CELL(_scmi_id, _id, _name) \ 22 [(_scmi_id)] = { \ 23 .reset_id = (_id), \ 24 .name = (_name), \ 25 } 26 27 #define RST_SCMI_USB1 0 28 #define RST_SCMI_USB2 1 29 #define RST_SCMI_USB3 2 30 31 struct sam_scmi_rd { 32 unsigned int reset_id; 33 const char *name; 34 struct rstctrl *rstctrl; 35 }; 36 37 static struct sam_scmi_rd sam_scmi_reset_domain[] = { 38 #ifdef CFG_SAMA7G5 39 RESET_CELL(RST_SCMI_USB1, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 4, "USB1"), 40 RESET_CELL(RST_SCMI_USB2, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 5, "USB2"), 41 RESET_CELL(RST_SCMI_USB3, SHIFT_U32(0xE4, RESET_ID_SHIFT) | 6, "USB3"), 42 #endif 43 }; 44 45 struct channel_resources { 46 struct scmi_msg_channel *channel; 47 struct sam_scmi_rd *rd; 48 size_t rd_count; 49 }; 50 51 static const struct channel_resources scmi_channel[] = { 52 [0] = { 53 .channel = &(struct scmi_msg_channel){ 54 .shm_addr = { .pa = CFG_SCMI_SHMEM_START }, 55 .shm_size = SMT_BUF_SLOT_SIZE, 56 }, 57 .rd = sam_scmi_reset_domain, 58 .rd_count = ARRAY_SIZE(sam_scmi_reset_domain), 59 }, 60 }; 61 62 static const struct channel_resources *find_resource(unsigned int channel_id) 63 { 64 assert(channel_id < ARRAY_SIZE(scmi_channel)); 65 66 return scmi_channel + channel_id; 67 } 68 69 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int channel_id) 70 { 71 const size_t max_id = ARRAY_SIZE(scmi_channel); 72 unsigned int confined_id = confine_array_index(channel_id, max_id); 73 74 if (channel_id >= max_id) 75 return NULL; 76 77 return find_resource(confined_id)->channel; 78 } 79 80 static const char vendor[] = "Microchip"; 81 static const char sub_vendor[] = ""; 82 83 const char *plat_scmi_vendor_name(void) 84 { 85 return vendor; 86 } 87 88 const char *plat_scmi_sub_vendor_name(void) 89 { 90 return sub_vendor; 91 } 92 93 /* Currently supporting only SCMI Base protocol */ 94 static const uint8_t plat_protocol_list[] = { 95 SCMI_PROTOCOL_ID_CLOCK, 96 SCMI_PROTOCOL_ID_RESET_DOMAIN, 97 0 /* Null termination */ 98 }; 99 100 size_t plat_scmi_protocol_count(void) 101 { 102 return ARRAY_SIZE(plat_protocol_list) - 1; 103 } 104 105 const uint8_t *plat_scmi_protocol_list(unsigned int channel_id __unused) 106 { 107 return plat_protocol_list; 108 } 109 110 struct sam_pmc_clk { 111 unsigned int scmi_id; 112 unsigned int pmc_type; 113 unsigned int pmc_id; 114 }; 115 116 #ifdef CFG_SAMA7G5 117 static const struct sam_pmc_clk pmc_clks[] = { 118 { 119 .scmi_id = AT91_SCMI_CLK_CORE_MCK, 120 .pmc_type = PMC_TYPE_CORE, 121 .pmc_id = PMC_MCK 122 }, 123 { 124 .scmi_id = AT91_SCMI_CLK_CORE_UTMI, 125 .pmc_type = PMC_TYPE_CORE, 126 .pmc_id = PMC_UTMI 127 }, 128 { 129 .scmi_id = AT91_SCMI_CLK_CORE_CPUPLLCK, 130 .pmc_type = PMC_TYPE_CORE, 131 .pmc_id = PMC_CPUPLL 132 }, 133 { 134 .scmi_id = AT91_SCMI_CLK_CORE_MAIN, 135 .pmc_type = PMC_TYPE_CORE, 136 .pmc_id = PMC_MAIN 137 }, 138 { 139 .scmi_id = AT91_SCMI_CLK_CORE_SYSPLLCK, 140 .pmc_type = PMC_TYPE_CORE, 141 .pmc_id = PMC_SYSPLL 142 }, 143 144 { 145 .scmi_id = AT91_SCMI_CLK_CORE_AUDIOPLLCK, 146 .pmc_type = PMC_TYPE_CORE, 147 .pmc_id = PMC_AUDIOPMCPLL 148 }, 149 150 { 151 .scmi_id = AT91_SCMI_CLK_CORE_MCK_PRES, 152 .pmc_type = PMC_TYPE_CORE, 153 .pmc_id = PMC_MCK_PRES 154 }, 155 { 156 .scmi_id = AT91_SCMI_CLK_CORE_DDRPLLCK, 157 .pmc_type = PMC_TYPE_CORE, 158 .pmc_id = PMC_DDRPLL 159 }, 160 { 161 .scmi_id = AT91_SCMI_CLK_CORE_IMGPLLCK, 162 .pmc_type = PMC_TYPE_CORE, 163 .pmc_id = PMC_IMGPLL 164 }, 165 { 166 .scmi_id = AT91_SCMI_CLK_CORE_ETHPLLCK, 167 .pmc_type = PMC_TYPE_CORE, 168 .pmc_id = PMC_ETHPLL 169 }, 170 { 171 .scmi_id = AT91_SCMI_CLK_UTMI1, 172 .pmc_type = PMC_TYPE_CORE, 173 .pmc_id = PMC_UTMI1 174 }, 175 { 176 .scmi_id = AT91_SCMI_CLK_UTMI2, 177 .pmc_type = PMC_TYPE_CORE, 178 .pmc_id = PMC_UTMI2 179 }, 180 { 181 .scmi_id = AT91_SCMI_CLK_UTMI3, 182 .pmc_type = PMC_TYPE_CORE, 183 .pmc_id = PMC_UTMI3 184 }, 185 { 186 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK0, 187 .pmc_type = PMC_TYPE_SYSTEM, 188 .pmc_id = 8 189 }, 190 { 191 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK1, 192 .pmc_type = PMC_TYPE_SYSTEM, 193 .pmc_id = 9 194 }, 195 { 196 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK2, 197 .pmc_type = PMC_TYPE_SYSTEM, 198 .pmc_id = 10 199 }, 200 { 201 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK3, 202 .pmc_type = PMC_TYPE_SYSTEM, 203 .pmc_id = 11 204 }, 205 { 206 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK4, 207 .pmc_type = PMC_TYPE_SYSTEM, 208 .pmc_id = 12 209 }, 210 { 211 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK5, 212 .pmc_type = PMC_TYPE_SYSTEM, 213 .pmc_id = 13 214 }, 215 { 216 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK6, 217 .pmc_type = PMC_TYPE_SYSTEM, 218 .pmc_id = 14 219 }, 220 { 221 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK7, 222 .pmc_type = PMC_TYPE_SYSTEM, 223 .pmc_id = 15 224 }, 225 { 226 .scmi_id = AT91_SCMI_CLK_PERIPH_ASRC_CLK, 227 .pmc_type = PMC_TYPE_PERIPHERAL, 228 .pmc_id = ID_ASRC 229 }, 230 { 231 .scmi_id = AT91_SCMI_CLK_GCK_ASRC_GCLK, 232 .pmc_type = PMC_TYPE_GCK, 233 .pmc_id = ID_ASRC 234 }, 235 { 236 .scmi_id = AT91_SCMI_CLK_PERIPH_CSI_CLK, 237 .pmc_type = PMC_TYPE_PERIPHERAL, 238 .pmc_id = ID_CSI 239 }, 240 { 241 .scmi_id = AT91_SCMI_CLK_GCK_CSI_GCLK, 242 .pmc_type = PMC_TYPE_GCK, 243 .pmc_id = ID_CSI 244 }, 245 { 246 .scmi_id = AT91_SCMI_CLK_PERIPH_CSI2DC_CLK, 247 .pmc_type = PMC_TYPE_PERIPHERAL, 248 .pmc_id = ID_CSI2DC 249 }, 250 { 251 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB0_CLK, 252 .pmc_type = PMC_TYPE_PERIPHERAL, 253 .pmc_id = ID_GMAC0 254 }, 255 { 256 .scmi_id = AT91_SCMI_CLK_GCK_MACB0_GCLK, 257 .pmc_type = PMC_TYPE_GCK, 258 .pmc_id = ID_GMAC0 259 }, 260 { 261 .scmi_id = AT91_SCMI_CLK_GCK_MACB0_TSU, 262 .pmc_type = PMC_TYPE_GCK, 263 .pmc_id = ID_GMAC0_TSU 264 }, 265 { 266 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB1_CLK, 267 .pmc_type = PMC_TYPE_PERIPHERAL, 268 .pmc_id = ID_GMAC1 269 }, 270 { 271 .scmi_id = AT91_SCMI_CLK_GCK_MACB1_GCLK, 272 .pmc_type = PMC_TYPE_GCK, 273 .pmc_id = ID_GMAC1 274 }, 275 { 276 .scmi_id = AT91_SCMI_CLK_GCK_MACB1_TSU, 277 .pmc_type = PMC_TYPE_GCK, 278 .pmc_id = ID_GMAC1_TSU 279 }, 280 { 281 .scmi_id = AT91_SCMI_CLK_PERIPH_TDES_CLK, 282 .pmc_type = PMC_TYPE_PERIPHERAL, 283 .pmc_id = ID_TDES 284 }, 285 { 286 .scmi_id = AT91_SCMI_CLK_PERIPH_HSMC_CLK, 287 .pmc_type = PMC_TYPE_PERIPHERAL, 288 .pmc_id = ID_HSMC 289 }, 290 { 291 .scmi_id = AT91_SCMI_CLK_PERIPH_PIOA_CLK, 292 .pmc_type = PMC_TYPE_PERIPHERAL, 293 .pmc_id = ID_PIOA 294 }, 295 { 296 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX0_CLK, 297 .pmc_type = PMC_TYPE_PERIPHERAL, 298 .pmc_id = ID_FLEXCOM0 299 }, 300 { 301 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX1_CLK, 302 .pmc_type = PMC_TYPE_PERIPHERAL, 303 .pmc_id = ID_FLEXCOM1 304 }, 305 { 306 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX2_CLK, 307 .pmc_type = PMC_TYPE_PERIPHERAL, 308 .pmc_id = ID_FLEXCOM2 309 }, 310 { 311 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX3_CLK, 312 .pmc_type = PMC_TYPE_PERIPHERAL, 313 .pmc_id = ID_FLEXCOM3 314 }, 315 { 316 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX4_CLK, 317 .pmc_type = PMC_TYPE_PERIPHERAL, 318 .pmc_id = ID_FLEXCOM4 319 }, 320 { 321 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX5_CLK, 322 .pmc_type = PMC_TYPE_PERIPHERAL, 323 .pmc_id = ID_FLEXCOM5 324 }, 325 { 326 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX6_CLK, 327 .pmc_type = PMC_TYPE_PERIPHERAL, 328 .pmc_id = ID_FLEXCOM6 329 }, 330 { 331 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX7_CLK, 332 .pmc_type = PMC_TYPE_PERIPHERAL, 333 .pmc_id = ID_FLEXCOM7 334 }, 335 { 336 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX8_CLK, 337 .pmc_type = PMC_TYPE_PERIPHERAL, 338 .pmc_id = ID_FLEXCOM8 339 }, 340 { 341 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX9_CLK, 342 .pmc_type = PMC_TYPE_PERIPHERAL, 343 .pmc_id = ID_FLEXCOM9 344 }, 345 { 346 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX10_CLK, 347 .pmc_type = PMC_TYPE_PERIPHERAL, 348 .pmc_id = ID_FLEXCOM10 349 }, 350 { 351 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX11_CLK, 352 .pmc_type = PMC_TYPE_PERIPHERAL, 353 .pmc_id = ID_FLEXCOM11 354 }, 355 { 356 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB0_CLK, 357 .pmc_type = PMC_TYPE_PERIPHERAL, 358 .pmc_id = ID_TC0_CHANNEL0 359 }, 360 { 361 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB1_CLK, 362 .pmc_type = PMC_TYPE_PERIPHERAL, 363 .pmc_id = ID_TC1_CHANNEL0 364 }, 365 { 366 .scmi_id = AT91_SCMI_CLK_PERIPH_PWM_CLK, 367 .pmc_type = PMC_TYPE_PERIPHERAL, 368 .pmc_id = ID_PWM 369 }, 370 { 371 .scmi_id = AT91_SCMI_CLK_GCK_ADC_GCLK, 372 .pmc_type = PMC_TYPE_GCK, 373 .pmc_id = ID_ADC 374 }, 375 { 376 .scmi_id = AT91_SCMI_CLK_PERIPH_UHPHS_CLK, 377 .pmc_type = PMC_TYPE_PERIPHERAL, 378 .pmc_id = ID_UHPHS 379 }, 380 { 381 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHSA_CLK, 382 .pmc_type = PMC_TYPE_PERIPHERAL, 383 .pmc_id = ID_UDPHSA 384 }, 385 { 386 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHSB_CLK, 387 .pmc_type = PMC_TYPE_PERIPHERAL, 388 .pmc_id = ID_UDPHSB 389 }, 390 { 391 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC0_CLK, 392 .pmc_type = PMC_TYPE_PERIPHERAL, 393 .pmc_id = ID_SSC0 394 }, 395 { 396 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC1_CLK, 397 .pmc_type = PMC_TYPE_PERIPHERAL, 398 .pmc_id = ID_SSC1 399 }, 400 { 401 .scmi_id = AT91_SCMI_CLK_PERIPH_TRNG_CLK, 402 .pmc_type = PMC_TYPE_PERIPHERAL, 403 .pmc_id = ID_TRNG 404 }, 405 { 406 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMC0_CLK, 407 .pmc_type = PMC_TYPE_PERIPHERAL, 408 .pmc_id = ID_PDMC0 409 }, 410 { 411 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMC1_CLK, 412 .pmc_type = PMC_TYPE_PERIPHERAL, 413 .pmc_id = ID_PDMC1 414 }, 415 { 416 .scmi_id = AT91_SCMI_CLK_PERIPH_SECURAM_CLK, 417 .pmc_type = PMC_TYPE_PERIPHERAL, 418 .pmc_id = ID_SECURAM 419 }, 420 { 421 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S0_CLK, 422 .pmc_type = PMC_TYPE_PERIPHERAL, 423 .pmc_id = ID_I2SMCC0 424 }, 425 { 426 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S1_CLK, 427 .pmc_type = PMC_TYPE_PERIPHERAL, 428 .pmc_id = ID_I2SMCC1 429 }, 430 { 431 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN0_CLK, 432 .pmc_type = PMC_TYPE_PERIPHERAL, 433 .pmc_id = ID_MCAN0 434 }, 435 { 436 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN1_CLK, 437 .pmc_type = PMC_TYPE_PERIPHERAL, 438 .pmc_id = ID_MCAN1 439 }, 440 { 441 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN2_CLK, 442 .pmc_type = PMC_TYPE_PERIPHERAL, 443 .pmc_id = ID_MCAN2 444 }, 445 { 446 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN3_CLK, 447 .pmc_type = PMC_TYPE_PERIPHERAL, 448 .pmc_id = ID_MCAN3 449 }, 450 { 451 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN4_CLK, 452 .pmc_type = PMC_TYPE_PERIPHERAL, 453 .pmc_id = ID_MCAN4 454 }, 455 { 456 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN5_CLK, 457 .pmc_type = PMC_TYPE_PERIPHERAL, 458 .pmc_id = ID_MCAN5 459 }, 460 { 461 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA0_CLK, 462 .pmc_type = PMC_TYPE_PERIPHERAL, 463 .pmc_id = ID_XDMAC0 464 }, 465 { 466 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA1_CLK, 467 .pmc_type = PMC_TYPE_PERIPHERAL, 468 .pmc_id = ID_XDMAC1 469 }, 470 { 471 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA2_CLK, 472 .pmc_type = PMC_TYPE_PERIPHERAL, 473 .pmc_id = ID_XDMAC2 474 }, 475 { 476 .scmi_id = AT91_SCMI_CLK_PERIPH_SPDIFRX_CLK, 477 .pmc_type = PMC_TYPE_PERIPHERAL, 478 .pmc_id = ID_SPDIFRX 479 }, 480 { 481 .scmi_id = AT91_SCMI_CLK_PERIPH_SPDIFTX_CLK, 482 .pmc_type = PMC_TYPE_PERIPHERAL, 483 .pmc_id = ID_SPDIFTX 484 }, 485 { 486 .scmi_id = AT91_SCMI_CLK_GCK_SPDIFRX_GCLK, 487 .pmc_type = PMC_TYPE_GCK, 488 .pmc_id = ID_SPDIFRX 489 }, 490 { 491 .scmi_id = AT91_SCMI_CLK_GCK_SPDIFTX_GCLK, 492 .pmc_type = PMC_TYPE_GCK, 493 .pmc_id = ID_SPDIFTX 494 }, 495 { 496 .scmi_id = AT91_SCMI_CLK_PERIPH_AES_CLK, 497 .pmc_type = PMC_TYPE_PERIPHERAL, 498 .pmc_id = ID_AES 499 }, 500 { 501 .scmi_id = AT91_SCMI_CLK_PERIPH_AESB_CLK, 502 .pmc_type = PMC_TYPE_PERIPHERAL, 503 .pmc_id = ID_TZAESBASC 504 }, 505 { 506 .scmi_id = AT91_SCMI_CLK_PERIPH_SHA_CLK, 507 .pmc_type = PMC_TYPE_PERIPHERAL, 508 .pmc_id = ID_SHA 509 }, 510 { 511 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK, 512 .pmc_type = PMC_TYPE_PERIPHERAL, 513 .pmc_id = ID_SDMMC0 514 }, 515 { 516 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK, 517 .pmc_type = PMC_TYPE_PERIPHERAL, 518 .pmc_id = ID_SDMMC1 519 }, 520 { 521 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC2_HCLK, 522 .pmc_type = PMC_TYPE_PERIPHERAL, 523 .pmc_id = ID_SDMMC2 524 }, 525 { 526 .scmi_id = AT91_SCMI_CLK_PERIPH_ISC_CLK, 527 .pmc_type = PMC_TYPE_PERIPHERAL, 528 .pmc_id = ID_ISC 529 }, 530 { 531 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI0_CLK, 532 .pmc_type = PMC_TYPE_PERIPHERAL, 533 .pmc_id = ID_QSPI0 534 }, 535 { 536 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI1_CLK, 537 .pmc_type = PMC_TYPE_PERIPHERAL, 538 .pmc_id = ID_QSPI1 539 }, 540 { 541 .scmi_id = AT91_SCMI_CLK_GCK_QSPI0_GCLK, 542 .pmc_type = PMC_TYPE_GCK, 543 .pmc_id = ID_QSPI0 544 }, 545 { 546 .scmi_id = AT91_SCMI_CLK_GCK_QSPI1_GCLK, 547 .pmc_type = PMC_TYPE_GCK, 548 .pmc_id = ID_QSPI1 549 }, 550 { 551 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC0_GCLK, 552 .pmc_type = PMC_TYPE_GCK, 553 .pmc_id = ID_SDMMC0 554 }, 555 { 556 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC1_GCLK, 557 .pmc_type = PMC_TYPE_GCK, 558 .pmc_id = ID_SDMMC1 559 }, 560 { 561 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC2_GCLK, 562 .pmc_type = PMC_TYPE_GCK, 563 .pmc_id = ID_SDMMC2 564 }, 565 { 566 .scmi_id = AT91_SCMI_CLK_GCK_TCB0_GCLK, 567 .pmc_type = PMC_TYPE_GCK, 568 .pmc_id = ID_TC0_CHANNEL0 569 }, 570 { 571 .scmi_id = AT91_SCMI_CLK_GCK_TCB1_GCLK, 572 .pmc_type = PMC_TYPE_GCK, 573 .pmc_id = ID_TC1_CHANNEL0 574 }, 575 { 576 .scmi_id = AT91_SCMI_CLK_GCK_I2S0_GCLK, 577 .pmc_type = PMC_TYPE_GCK, 578 .pmc_id = ID_I2SMCC0 579 }, 580 { 581 .scmi_id = AT91_SCMI_CLK_GCK_I2S1_GCLK, 582 .pmc_type = PMC_TYPE_GCK, 583 .pmc_id = ID_I2SMCC1 584 }, 585 { 586 .scmi_id = AT91_SCMI_CLK_GCK_CAN0_GCLK, 587 .pmc_type = PMC_TYPE_GCK, 588 .pmc_id = ID_MCAN0 589 }, 590 { 591 .scmi_id = AT91_SCMI_CLK_GCK_CAN1_GCLK, 592 .pmc_type = PMC_TYPE_GCK, 593 .pmc_id = ID_MCAN1 594 }, 595 { 596 .scmi_id = AT91_SCMI_CLK_GCK_CAN2_GCLK, 597 .pmc_type = PMC_TYPE_GCK, 598 .pmc_id = ID_MCAN2 599 }, 600 { 601 .scmi_id = AT91_SCMI_CLK_GCK_CAN3_GCLK, 602 .pmc_type = PMC_TYPE_GCK, 603 .pmc_id = ID_MCAN3 604 }, 605 { 606 .scmi_id = AT91_SCMI_CLK_GCK_CAN4_GCLK, 607 .pmc_type = PMC_TYPE_GCK, 608 .pmc_id = ID_MCAN4 609 }, 610 { 611 .scmi_id = AT91_SCMI_CLK_GCK_CAN5_GCLK, 612 .pmc_type = PMC_TYPE_GCK, 613 .pmc_id = ID_MCAN5 614 }, 615 }; 616 #else 617 static const struct sam_pmc_clk pmc_clks[] = { 618 { 619 .scmi_id = AT91_SCMI_CLK_CORE_MCK, 620 .pmc_type = PMC_TYPE_CORE, 621 .pmc_id = PMC_MCK 622 }, 623 { 624 .scmi_id = AT91_SCMI_CLK_CORE_UTMI, 625 .pmc_type = PMC_TYPE_CORE, 626 .pmc_id = PMC_UTMI 627 }, 628 { 629 .scmi_id = AT91_SCMI_CLK_CORE_MAIN, 630 .pmc_type = PMC_TYPE_CORE, 631 .pmc_id = PMC_MAIN 632 }, 633 { 634 .scmi_id = AT91_SCMI_CLK_CORE_MCK2, 635 .pmc_type = PMC_TYPE_CORE, 636 .pmc_id = PMC_MCK2 637 }, 638 { 639 .scmi_id = AT91_SCMI_CLK_CORE_I2S0_MUX, 640 .pmc_type = PMC_TYPE_CORE, 641 .pmc_id = PMC_I2S0_MUX 642 }, 643 { 644 .scmi_id = AT91_SCMI_CLK_CORE_I2S1_MUX, 645 .pmc_type = PMC_TYPE_CORE, 646 .pmc_id = PMC_I2S1_MUX 647 }, 648 { 649 .scmi_id = AT91_SCMI_CLK_CORE_PLLACK, 650 .pmc_type = PMC_TYPE_CORE, 651 .pmc_id = PMC_PLLACK 652 }, 653 { 654 .scmi_id = AT91_SCMI_CLK_CORE_AUDIOPLLCK, 655 .pmc_type = PMC_TYPE_CORE, 656 .pmc_id = PMC_AUDIOPLLCK 657 }, 658 { 659 .scmi_id = AT91_SCMI_CLK_CORE_MCK_PRES, 660 .pmc_type = PMC_TYPE_CORE, 661 .pmc_id = PMC_MCK_PRES 662 }, 663 { 664 .scmi_id = AT91_SCMI_CLK_SYSTEM_DDRCK, 665 .pmc_type = PMC_TYPE_SYSTEM, 666 .pmc_id = 2 667 }, 668 { 669 .scmi_id = AT91_SCMI_CLK_SYSTEM_LCDCK, 670 .pmc_type = PMC_TYPE_SYSTEM, 671 .pmc_id = 3 672 }, 673 { 674 .scmi_id = AT91_SCMI_CLK_SYSTEM_UHPCK, 675 .pmc_type = PMC_TYPE_SYSTEM, 676 .pmc_id = 6 677 }, 678 { 679 .scmi_id = AT91_SCMI_CLK_SYSTEM_UDPCK, 680 .pmc_type = PMC_TYPE_SYSTEM, 681 .pmc_id = 7 682 }, 683 { 684 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK0, 685 .pmc_type = PMC_TYPE_SYSTEM, 686 .pmc_id = 8 687 }, 688 { 689 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK1, 690 .pmc_type = PMC_TYPE_SYSTEM, 691 .pmc_id = 9 692 }, 693 { 694 .scmi_id = AT91_SCMI_CLK_SYSTEM_PCK2, 695 .pmc_type = PMC_TYPE_SYSTEM, 696 .pmc_id = 10 697 }, 698 { 699 .scmi_id = AT91_SCMI_CLK_SYSTEM_ISCCK, 700 .pmc_type = PMC_TYPE_SYSTEM, 701 .pmc_id = 18 702 }, 703 { 704 .scmi_id = AT91_SCMI_CLK_PERIPH_MACB0_CLK, 705 .pmc_type = PMC_TYPE_PERIPHERAL, 706 .pmc_id = 5 707 }, 708 { 709 .scmi_id = AT91_SCMI_CLK_PERIPH_TDES_CLK, 710 .pmc_type = PMC_TYPE_PERIPHERAL, 711 .pmc_id = 11 712 }, 713 { 714 .scmi_id = AT91_SCMI_CLK_PERIPH_MATRIX1_CLK, 715 .pmc_type = PMC_TYPE_PERIPHERAL, 716 .pmc_id = 14 717 }, 718 { 719 .scmi_id = AT91_SCMI_CLK_PERIPH_HSMC_CLK, 720 .pmc_type = PMC_TYPE_PERIPHERAL, 721 .pmc_id = 17 722 }, 723 { 724 .scmi_id = AT91_SCMI_CLK_PERIPH_PIOA_CLK, 725 .pmc_type = PMC_TYPE_PERIPHERAL, 726 .pmc_id = 18 727 }, 728 { 729 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX0_CLK, 730 .pmc_type = PMC_TYPE_PERIPHERAL, 731 .pmc_id = 19 732 }, 733 { 734 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX1_CLK, 735 .pmc_type = PMC_TYPE_PERIPHERAL, 736 .pmc_id = 20 737 }, 738 { 739 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX2_CLK, 740 .pmc_type = PMC_TYPE_PERIPHERAL, 741 .pmc_id = 21 742 }, 743 { 744 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX3_CLK, 745 .pmc_type = PMC_TYPE_PERIPHERAL, 746 .pmc_id = 22 747 }, 748 { 749 .scmi_id = AT91_SCMI_CLK_PERIPH_FLX4_CLK, 750 .pmc_type = PMC_TYPE_PERIPHERAL, 751 .pmc_id = 23 752 }, 753 { 754 .scmi_id = AT91_SCMI_CLK_PERIPH_UART0_CLK, 755 .pmc_type = PMC_TYPE_PERIPHERAL, 756 .pmc_id = 24 757 }, 758 { 759 .scmi_id = AT91_SCMI_CLK_PERIPH_UART1_CLK, 760 .pmc_type = PMC_TYPE_PERIPHERAL, 761 .pmc_id = 25 762 }, 763 { 764 .scmi_id = AT91_SCMI_CLK_PERIPH_UART2_CLK, 765 .pmc_type = PMC_TYPE_PERIPHERAL, 766 .pmc_id = 26 767 }, 768 { 769 .scmi_id = AT91_SCMI_CLK_PERIPH_UART3_CLK, 770 .pmc_type = PMC_TYPE_PERIPHERAL, 771 .pmc_id = 27 772 }, 773 { 774 .scmi_id = AT91_SCMI_CLK_PERIPH_UART4_CLK, 775 .pmc_type = PMC_TYPE_PERIPHERAL, 776 .pmc_id = 28 777 }, 778 { 779 .scmi_id = AT91_SCMI_CLK_PERIPH_TWI0_CLK, 780 .pmc_type = PMC_TYPE_PERIPHERAL, 781 .pmc_id = 29 782 }, 783 { 784 .scmi_id = AT91_SCMI_CLK_PERIPH_TWI1_CLK, 785 .pmc_type = PMC_TYPE_PERIPHERAL, 786 .pmc_id = 30 787 }, 788 { 789 .scmi_id = AT91_SCMI_CLK_PERIPH_SPI0_CLK, 790 .pmc_type = PMC_TYPE_PERIPHERAL, 791 .pmc_id = 33 792 }, 793 { 794 .scmi_id = AT91_SCMI_CLK_PERIPH_SPI1_CLK, 795 .pmc_type = PMC_TYPE_PERIPHERAL, 796 .pmc_id = 34 797 }, 798 { 799 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB0_CLK, 800 .pmc_type = PMC_TYPE_PERIPHERAL, 801 .pmc_id = 35 802 }, 803 { 804 .scmi_id = AT91_SCMI_CLK_PERIPH_TCB1_CLK, 805 .pmc_type = PMC_TYPE_PERIPHERAL, 806 .pmc_id = 36 807 }, 808 { 809 .scmi_id = AT91_SCMI_CLK_PERIPH_PWM_CLK, 810 .pmc_type = PMC_TYPE_PERIPHERAL, 811 .pmc_id = 38 812 }, 813 { 814 .scmi_id = AT91_SCMI_CLK_PERIPH_ADC_CLK, 815 .pmc_type = PMC_TYPE_PERIPHERAL, 816 .pmc_id = 40 817 }, 818 { 819 .scmi_id = AT91_SCMI_CLK_PERIPH_UHPHS_CLK, 820 .pmc_type = PMC_TYPE_PERIPHERAL, 821 .pmc_id = 41 822 }, 823 { 824 .scmi_id = AT91_SCMI_CLK_PERIPH_UDPHS_CLK, 825 .pmc_type = PMC_TYPE_PERIPHERAL, 826 .pmc_id = 42 827 }, 828 { 829 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC0_CLK, 830 .pmc_type = PMC_TYPE_PERIPHERAL, 831 .pmc_id = 43 832 }, 833 { 834 .scmi_id = AT91_SCMI_CLK_PERIPH_SSC1_CLK, 835 .pmc_type = PMC_TYPE_PERIPHERAL, 836 .pmc_id = 44 837 }, 838 { 839 .scmi_id = AT91_SCMI_CLK_PERIPH_TRNG_CLK, 840 .pmc_type = PMC_TYPE_PERIPHERAL, 841 .pmc_id = 47 842 }, 843 { 844 .scmi_id = AT91_SCMI_CLK_PERIPH_PDMIC_CLK, 845 .pmc_type = PMC_TYPE_PERIPHERAL, 846 .pmc_id = 48 847 }, 848 { 849 .scmi_id = AT91_SCMI_CLK_PERIPH_SECURAM_CLK, 850 .pmc_type = PMC_TYPE_PERIPHERAL, 851 .pmc_id = 51 852 }, 853 { 854 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S0_CLK, 855 .pmc_type = PMC_TYPE_PERIPHERAL, 856 .pmc_id = 54 857 }, 858 { 859 .scmi_id = AT91_SCMI_CLK_PERIPH_I2S1_CLK, 860 .pmc_type = PMC_TYPE_PERIPHERAL, 861 .pmc_id = 55 862 }, 863 { 864 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN0_CLK, 865 .pmc_type = PMC_TYPE_PERIPHERAL, 866 .pmc_id = 56 867 }, 868 { 869 .scmi_id = AT91_SCMI_CLK_PERIPH_CAN1_CLK, 870 .pmc_type = PMC_TYPE_PERIPHERAL, 871 .pmc_id = 57 872 }, 873 { 874 .scmi_id = AT91_SCMI_CLK_PERIPH_PTC_CLK, 875 .pmc_type = PMC_TYPE_PERIPHERAL, 876 .pmc_id = 58 877 }, 878 { 879 .scmi_id = AT91_SCMI_CLK_PERIPH_CLASSD_CLK, 880 .pmc_type = PMC_TYPE_PERIPHERAL, 881 .pmc_id = 59 882 }, 883 { 884 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA0_CLK, 885 .pmc_type = PMC_TYPE_PERIPHERAL, 886 .pmc_id = 6 887 }, 888 { 889 .scmi_id = AT91_SCMI_CLK_PERIPH_DMA1_CLK, 890 .pmc_type = PMC_TYPE_PERIPHERAL, 891 .pmc_id = 7 892 }, 893 { 894 .scmi_id = AT91_SCMI_CLK_PERIPH_AES_CLK, 895 .pmc_type = PMC_TYPE_PERIPHERAL, 896 .pmc_id = 9 897 }, 898 { 899 .scmi_id = AT91_SCMI_CLK_PERIPH_AESB_CLK, 900 .pmc_type = PMC_TYPE_PERIPHERAL, 901 .pmc_id = 10 902 }, 903 { 904 .scmi_id = AT91_SCMI_CLK_PERIPH_SHA_CLK, 905 .pmc_type = PMC_TYPE_PERIPHERAL, 906 .pmc_id = 12 907 }, 908 { 909 .scmi_id = AT91_SCMI_CLK_PERIPH_MPDDR_CLK, 910 .pmc_type = PMC_TYPE_PERIPHERAL, 911 .pmc_id = 13 912 }, 913 { 914 .scmi_id = AT91_SCMI_CLK_PERIPH_MATRIX0_CLK, 915 .pmc_type = PMC_TYPE_PERIPHERAL, 916 .pmc_id = 15 917 }, 918 { 919 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK, 920 .pmc_type = PMC_TYPE_PERIPHERAL, 921 .pmc_id = 31 922 }, 923 { 924 .scmi_id = AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK, 925 .pmc_type = PMC_TYPE_PERIPHERAL, 926 .pmc_id = 32 927 }, 928 { 929 .scmi_id = AT91_SCMI_CLK_PERIPH_LCDC_CLK, 930 .pmc_type = PMC_TYPE_PERIPHERAL, 931 .pmc_id = 45 932 }, 933 { 934 .scmi_id = AT91_SCMI_CLK_PERIPH_ISC_CLK, 935 .pmc_type = PMC_TYPE_PERIPHERAL, 936 .pmc_id = 46 937 }, 938 { 939 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI0_CLK, 940 .pmc_type = PMC_TYPE_PERIPHERAL, 941 .pmc_id = 52 942 }, 943 { 944 .scmi_id = AT91_SCMI_CLK_PERIPH_QSPI1_CLK, 945 .pmc_type = PMC_TYPE_PERIPHERAL, 946 .pmc_id = 53 947 }, 948 { 949 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC0_GCLK, 950 .pmc_type = PMC_TYPE_GCK, 951 .pmc_id = 31 952 }, 953 { 954 .scmi_id = AT91_SCMI_CLK_GCK_SDMMC1_GCLK, 955 .pmc_type = PMC_TYPE_GCK, 956 .pmc_id = 32 957 }, 958 { 959 .scmi_id = AT91_SCMI_CLK_GCK_TCB0_GCLK, 960 .pmc_type = PMC_TYPE_GCK, 961 .pmc_id = 35 962 }, 963 { 964 .scmi_id = AT91_SCMI_CLK_GCK_TCB1_GCLK, 965 .pmc_type = PMC_TYPE_GCK, 966 .pmc_id = 36 967 }, 968 { 969 .scmi_id = AT91_SCMI_CLK_GCK_PWM_GCLK, 970 .pmc_type = PMC_TYPE_GCK, 971 .pmc_id = 38 972 }, 973 { 974 .scmi_id = AT91_SCMI_CLK_GCK_ISC_GCLK, 975 .pmc_type = PMC_TYPE_GCK, 976 .pmc_id = 46 977 }, 978 { 979 .scmi_id = AT91_SCMI_CLK_GCK_PDMIC_GCLK, 980 .pmc_type = PMC_TYPE_GCK, 981 .pmc_id = 48 982 }, 983 { 984 .scmi_id = AT91_SCMI_CLK_GCK_I2S0_GCLK, 985 .pmc_type = PMC_TYPE_GCK, 986 .pmc_id = 54 987 }, 988 { 989 .scmi_id = AT91_SCMI_CLK_GCK_I2S1_GCLK, 990 .pmc_type = PMC_TYPE_GCK, 991 .pmc_id = 55 992 }, 993 { 994 .scmi_id = AT91_SCMI_CLK_GCK_CAN0_GCLK, 995 .pmc_type = PMC_TYPE_GCK, 996 .pmc_id = 56 997 }, 998 { 999 .scmi_id = AT91_SCMI_CLK_GCK_CAN1_GCLK, 1000 .pmc_type = PMC_TYPE_GCK, 1001 .pmc_id = 57 1002 }, 1003 { 1004 .scmi_id = AT91_SCMI_CLK_GCK_CLASSD_GCLK, 1005 .pmc_type = PMC_TYPE_GCK, 1006 .pmc_id = 59 1007 }, 1008 { 1009 .scmi_id = AT91_SCMI_CLK_PROG_PROG0, 1010 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1011 .pmc_id = 0 1012 }, 1013 { 1014 .scmi_id = AT91_SCMI_CLK_PROG_PROG1, 1015 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1016 .pmc_id = 1 1017 }, 1018 { 1019 .scmi_id = AT91_SCMI_CLK_PROG_PROG2, 1020 .pmc_type = PMC_TYPE_PROGRAMMABLE, 1021 .pmc_id = 2 1022 }, 1023 }; 1024 #endif 1025 1026 static TEE_Result sam_init_scmi_clk(void) 1027 { 1028 unsigned int i = 0; 1029 struct clk *clk = NULL; 1030 TEE_Result res = TEE_ERROR_GENERIC; 1031 const struct sam_pmc_clk *pmc_clk = NULL; 1032 1033 for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { 1034 pmc_clk = &pmc_clks[i]; 1035 res = at91_pmc_clk_get(pmc_clk->pmc_type, pmc_clk->pmc_id, 1036 &clk); 1037 if (res) { 1038 EMSG("Failed to get PMC clock type %u, id %u", 1039 pmc_clk->pmc_type, pmc_clk->pmc_id); 1040 return res; 1041 } 1042 res = scmi_clk_add(clk, 0, pmc_clk->scmi_id); 1043 if (res) { 1044 EMSG("Failed to add PMC SCMI clock id %u", 1045 pmc_clk->scmi_id); 1046 return res; 1047 } 1048 } 1049 1050 clk = at91_sckc_clk_get(); 1051 if (!clk) 1052 return TEE_ERROR_GENERIC; 1053 1054 res = scmi_clk_add(clk, 0, AT91_SCMI_CLK_SCKC_SLOWCK_32K); 1055 if (res) { 1056 EMSG("Failed to add slow clock to SCMI clocks"); 1057 return res; 1058 } 1059 1060 clk = at91_cpu_opp_clk_get(); 1061 if (clk) { 1062 res = scmi_clk_add(clk, 0, AT91_SCMI_CLK_CPU_OPP); 1063 if (res) { 1064 EMSG("Failed to add CPU OPP clock to SCMI clocks"); 1065 return res; 1066 } 1067 } 1068 1069 return TEE_SUCCESS; 1070 } 1071 1072 static struct sam_scmi_rd *find_rd(unsigned int channel_id, 1073 unsigned int scmi_id) 1074 { 1075 const struct channel_resources *resource = find_resource(channel_id); 1076 1077 if (resource && scmi_id < resource->rd_count) 1078 return &resource->rd[scmi_id]; 1079 1080 return NULL; 1081 } 1082 1083 int32_t plat_scmi_rd_set_state(unsigned int channel_id, unsigned int scmi_id, 1084 bool assert_not_deassert) 1085 { 1086 const struct sam_scmi_rd *rd = find_rd(channel_id, scmi_id); 1087 TEE_Result res = TEE_ERROR_GENERIC; 1088 1089 if (!rd) 1090 return SCMI_NOT_FOUND; 1091 1092 if (!rd->rstctrl) 1093 return SCMI_DENIED; 1094 1095 if (assert_not_deassert) { 1096 FMSG("SCMI reset %u set", scmi_id); 1097 res = rstctrl_assert(rd->rstctrl); 1098 } else { 1099 FMSG("SCMI reset %u release", scmi_id); 1100 res = rstctrl_deassert(rd->rstctrl); 1101 } 1102 1103 if (res) 1104 return SCMI_HARDWARE_ERROR; 1105 1106 return SCMI_SUCCESS; 1107 } 1108 1109 size_t plat_scmi_rd_count(unsigned int channel_id) 1110 { 1111 const struct channel_resources *resource = find_resource(channel_id); 1112 1113 if (!resource) 1114 return 0; 1115 1116 return resource->rd_count; 1117 } 1118 1119 /* 1120 * Initialize platform SCMI resources 1121 */ 1122 static TEE_Result sam_init_scmi_server(void) 1123 { 1124 size_t i = 0; 1125 size_t j = 0; 1126 1127 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 1128 const struct channel_resources *res = scmi_channel + i; 1129 struct scmi_msg_channel *chan = res->channel; 1130 1131 /* Enforce non-secure shm mapped as device memory */ 1132 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 1133 MEM_AREA_IO_NSEC, 1); 1134 assert(chan->shm_addr.va); 1135 1136 scmi_smt_init_agent_channel(chan); 1137 1138 for (j = 0; j < res->rd_count; j++) { 1139 struct sam_scmi_rd *rd = &res->rd[j]; 1140 struct rstctrl *rstctrl = NULL; 1141 1142 rstctrl = sam_get_rstctrl(rd->reset_id); 1143 assert(rstctrl); 1144 if (rstctrl_get_exclusive(rstctrl)) 1145 continue; 1146 1147 rd->rstctrl = rstctrl; 1148 } 1149 } 1150 1151 return sam_init_scmi_clk(); 1152 } 1153 1154 driver_init_late(sam_init_scmi_server); 1155