1 /* 2 * Copyright (c) 2015, Atmel Corporation 3 * Copyright (c) 2017, Timesys Corporation 4 * 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Atmel's name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef SAMA5D2_H 28 #define SAMA5D2_H 29 30 /* 31 * Peripheral identifiers/interrupts. 32 */ 33 #define AT91C_ID_FIQ 0 /* FIQ Interrupt ID */ 34 #define AT91C_ID_1 1 /* Undefined/Reserved ID */ 35 #define AT91C_ID_ARM 2 /* Performance Monitor Unit */ 36 #define AT91C_ID_PIT 3 /* Periodic Interval Timer Interrupt */ 37 #define AT91C_ID_WDT 4 /* Watchdog Timer Interrupt */ 38 #define AT91C_ID_GMAC 5 /* Ethernet MAC */ 39 #define AT91C_ID_XDMAC0 6 /* DMA Controller 0 */ 40 #define AT91C_ID_XDMAC1 7 /* DMA Controller 1 */ 41 #define AT91C_ID_ICM 8 /* Integrity Check Monitor */ 42 #define AT91C_ID_AES 9 /* Advanced Encryption Standard */ 43 #define AT91C_ID_AESB 10 /* AES bridge */ 44 #define AT91C_ID_TDES 11 /* Triple Data Encryption Standard */ 45 #define AT91C_ID_SHA 12 /* SHA Signature */ 46 #define AT91C_ID_MPDDRC 13 /* MPDDR Controller */ 47 #define AT91C_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ 48 #define AT91C_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ 49 #define AT91C_ID_SECUMOD 16 /* Secure Module */ 50 #define AT91C_ID_HSMC 17 /* Multi-bit ECC interrupt */ 51 #define AT91C_ID_PIOA 18 /* Parallel I/O Controller A */ 52 #define AT91C_ID_FLEXCOM0 19 /* FLEXCOM0 */ 53 #define AT91C_ID_FLEXCOM1 20 /* FLEXCOM1 */ 54 #define AT91C_ID_FLEXCOM2 21 /* FLEXCOM2 */ 55 #define AT91C_ID_FLEXCOM3 22 /* FLEXCOM3 */ 56 #define AT91C_ID_FLEXCOM4 23 /* FLEXCOM4 */ 57 #define AT91C_ID_UART0 24 /* UART0 */ 58 #define AT91C_ID_UART1 25 /* UART1 */ 59 #define AT91C_ID_UART2 26 /* UART2 */ 60 #define AT91C_ID_UART3 27 /* UART3 */ 61 #define AT91C_ID_UART4 28 /* UART4 */ 62 #define AT91C_ID_TWI0 29 /* Two-wire Interface 0 */ 63 #define AT91C_ID_TWI1 30 /* Two-wire Interface 1 */ 64 #define AT91C_ID_SDMMC0 31 /* SDMMC Controller 0 */ 65 #define AT91C_ID_SDMMC1 32 /* SDMMC Controller 1 */ 66 #define AT91C_ID_SPI0 33 /* Serial Peripheral Interface 0 */ 67 #define AT91C_ID_SPI1 34 /* Serial Peripheral Interface 1 */ 68 #define AT91C_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ 69 #define AT91C_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ 70 /* 37 */ 71 #define AT91C_ID_PWM 38 /* PWM Controller0 (ch. 0,1,2,3) */ 72 /* 39 */ 73 #define AT91C_ID_ADC 40 /* Touch Screen ADC Controller */ 74 #define AT91C_ID_UHPHS 41 /* USB Host High Speed */ 75 #define AT91C_ID_UDPHS 42 /* USB Device High Speed */ 76 #define AT91C_ID_SSC0 43 /* Serial Synchronous Controller 0 */ 77 #define AT91C_ID_SSC1 44 /* Serial Synchronous Controller 1 */ 78 #define AT91C_ID_LCDC 45 /* LCD Controller */ 79 #define AT91C_ID_ISI 46 /* Image Sensor Interface */ 80 #define AT91C_ID_TRNG 47 /* True Random Number Generator */ 81 #define AT91C_ID_PDMIC 48 /* PDM Interface Controller */ 82 #define AT91C_ID_IRQ 49 /* IRQ Interrupt ID */ 83 #define AT91C_ID_SFC 50 /* Fuse Controller */ 84 #define AT91C_ID_SECURAM 51 /* Secure RAM */ 85 #define AT91C_ID_QSPI0 52 /* QSPI0 */ 86 #define AT91C_ID_QSPI1 53 /* QSPI1 */ 87 #define AT91C_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ 88 #define AT91C_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ 89 #define AT91C_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ 90 #define AT91C_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ 91 #define AT91C_ID_PTC 58 /* Peripheral Touch Controller */ 92 #define AT91C_ID_CLASSD 59 /* Audio Class D Amplifier */ 93 #define AT91C_ID_SFR 60 /* Special Function Register */ 94 #define AT91C_ID_SAIC 61 /* Secured AIC */ 95 #define AT91C_ID_AIC 62 /* Advanced Interrupt Controller */ 96 #define AT91C_ID_L2CC 63 /* L2 Cache Controller */ 97 #define AT91C_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ 98 #define AT91C_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ 99 #define AT91C_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ 100 #define AT91C_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ 101 #define AT91C_ID_PIOB 68 /* Parallel I/O Controller B */ 102 #define AT91C_ID_PIOC 69 /* Parallel I/O Controller C */ 103 #define AT91C_ID_PIOD 70 /* Parallel I/O Controller D */ 104 #define AT91C_ID_SDMMC0_TIMER 71 /* SDMMC0 Timer */ 105 #define AT91C_ID_SDMMC1_TIMER 72 /* SDMMC1 Timer */ 106 /* 73 */ 107 #define AT91C_ID_SYS 74 /* System Controller Interrupt */ 108 #define AT91C_ID_ACC 75 /* Analog Comparator */ 109 #define AT91C_ID_RXLP 76 /* UART Low-Power */ 110 #define AT91C_ID_SFRBU 77 /* Special Function Register BackUp */ 111 #define AT91C_ID_CHIPID 78 /* Chip ID */ 112 113 #define AT91C_ID_COUNTS (AT91C_ID_CHIPID + 1) 114 115 /* 116 * User Peripherals physical base addresses. 117 */ 118 #define AT91C_BASE_LCDC 0xf0000000 119 #define AT91C_BASE_XDMAC1 0xf0004000 120 #define AT91C_BASE_HXISI 0xf0008000 121 #define AT91C_BASE_MPDDRC 0xf000c000 122 #define AT91C_BASE_XDMAC0 0xf0010000 123 #define AT91C_BASE_PMC 0xf0014000 124 #define AT91C_BASE_MATRIX64 0xf0018000 /* MATRIX0 */ 125 #define AT91C_BASE_AESB 0xf001c000 126 #define AT91C_BASE_QSPI0 0xf0020000 127 #define AT91C_BASE_QSPI1 0xf0024000 128 #define AT91C_BASE_SHA 0xf0028000 129 #define AT91C_BASE_AES 0xf002c000 130 131 #define AT91C_BASE_SPI0 0xf8000000 132 #define AT91C_BASE_SSC0 0xf8004000 133 #define AT91C_BASE_GMAC 0xf8008000 134 #define AT91C_BASE_TC0 0xf800c000 135 #define AT91C_BASE_TC1 0xf8010000 136 #define AT91C_BASE_HSMC 0xf8014000 137 #define AT91C_BASE_PDMIC 0xf8018000 138 #define AT91C_BASE_UART0 0xf801c000 139 #define AT91C_BASE_UART1 0xf8020000 140 #define AT91C_BASE_UART2 0xf8024000 141 #define AT91C_BASE_TWI0 0xf8028000 142 #define AT91C_BASE_PWMC 0xf802c000 143 #define AT91C_BASE_SFR 0xf8030000 144 #define AT91C_BASE_FLEXCOM0 0xf8034000 145 #define AT91C_BASE_FLEXCOM1 0xf8038000 146 #define AT91C_BASE_SAIC 0xf803c000 147 #define AT91C_BASE_ICM 0xf8040000 148 #define AT91C_BASE_SECURAM 0xf8044000 149 #define AT91C_BASE_SYSC 0xf8048000 150 #define AT91C_BASE_ACC 0xf804a000 151 #define AT91C_BASE_SFC 0xf804c000 152 #define AT91C_BASE_I2SC0 0xf8050000 153 #define AT91C_BASE_CAN0 0xf8054000 154 155 #define AT91C_BASE_SPI1 0xfc000000 156 #define AT91C_BASE_SSC1 0xfc004000 157 #define AT91C_BASE_UART3 0xfc008000 158 #define AT91C_BASE_UART4 0xfc00c000 159 #define AT91C_BASE_FLEXCOM2 0xfc010000 160 #define AT91C_BASE_FLEXCOM3 0xfc014000 161 #define AT91C_BASE_FLEXCOM4 0xfc018000 162 #define AT91C_BASE_TRNG 0xfc01c000 163 #define AT91C_BASE_AIC 0xfc020000 164 #define AT91C_BASE_TWI1 0xfc028000 165 #define AT91C_BASE_UDPHS 0xfc02c000 166 #define AT91C_BASE_ADC 0xfc030000 167 168 #define AT91C_BASE_PIOA 0xfc038000 169 #define AT91C_BASE_MATRIX32 0xfc03c000 /* MATRIX1 */ 170 #define AT91C_BASE_SECUMOD 0xfc040000 171 #define AT91C_BASE_TDES 0xfc044000 172 #define AT91C_BASE_CLASSD 0xfc048000 173 #define AT91C_BASE_I2SC1 0xfc04c000 174 #define AT91C_BASE_CAN1 0xfc050000 175 #define AT91C_BASE_SFRBU 0xfc05c000 176 #define AT91C_BASE_CHIPID 0xfc069000 177 178 /* 179 * Address Memory Space 180 */ 181 #define AT91C_BASE_INTERNAL_MEM 0x00000000 182 #define AT91C_BASE_CS0 0x10000000 183 #define AT91C_BASE_DDRCS 0x20000000 184 #define AT91C_BASE_DDRCS_AES 0x40000000 185 #define AT91C_BASE_CS1 0x60000000 186 #define AT91C_BASE_CS2 0x70000000 187 #define AT91C_BASE_CS3 0x80000000 188 #define AT91C_BASE_QSPI0_AES_MEM 0x90000000 189 #define AT91C_BASE_QSPI1_AES_MEM 0x98000000 190 #define AT91C_BASE_SDHC0 0xa0000000 191 #define AT91C_BASE_SDHC1 0xb0000000 192 #define AT91C_BASE_NFC_CMD_REG 0xc0000000 193 #define AT91C_BASE_QSPI0_MEM 0xd0000000 194 #define AT91C_BASE_QSPI1_MEM 0xd8000000 195 #define AT91C_BASE_PERIPH 0xf0000000 196 197 /* 198 * Internal Memories 199 */ 200 #define AT91C_BASE_ROM 0x00000000 /* ROM */ 201 #define AT91C_BASE_ECC_ROM 0x00060000 /* ECC ROM */ 202 #define AT91C_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */ 203 #define AT91C_BASE_SRAM0 0x00200000 /* SRAM0 */ 204 #define AT91C_BASE_SRAM1 0x00220000 /* SRAM1 */ 205 #define AT91C_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */ 206 #define AT91C_BASE_UHP_OHCI 0x00400000 /* UHP OHCI */ 207 #define AT91C_BASE_UHP_EHCI 0x00500000 /* UHP EHCI */ 208 #define AT91C_BASE_AXI_MATRIX 0x00600000 /* AXI Maxtrix */ 209 #define AT91C_BASE_DAP 0x00700000 /* DAP */ 210 #define AT91C_BASE_PTC 0x00800000 /* PTC */ 211 #define AT91C_BASE_L2CC 0x00A00000 /* L2CC */ 212 213 /* 214 * Other misc defines 215 */ 216 #define AT91C_BASE_PMECC (AT91C_BASE_HSMC + 0x70) 217 #define AT91C_BASE_PMERRLOC (AT91C_BASE_HSMC + 0x500) 218 219 #define AT91_PMECC (AT91C_BASE_PMECC - AT91C_BASE_SYS) 220 #define AT91_PMERRLOC (AT91C_BASE_PMERRLOC - AT91C_BASE_SYS) 221 222 #define AT91C_BASE_PIOB (AT91C_BASE_PIOA + 0x40) 223 #define AT91C_BASE_PIOC (AT91C_BASE_PIOB + 0x40) 224 #define AT91C_BASE_PIOD (AT91C_BASE_PIOC + 0x40) 225 226 /* SYSC spawns */ 227 #define AT91C_BASE_RSTC AT91C_BASE_SYSC 228 #define AT91C_BASE_SHDC (AT91C_BASE_SYSC + 0x10) 229 #define AT91C_BASE_PITC (AT91C_BASE_SYSC + 0x30) 230 #define AT91C_BASE_WDT (AT91C_BASE_SYSC + 0x40) 231 #define AT91C_BASE_SCKCR (AT91C_BASE_SYSC + 0x50) 232 #define AT91C_BASE_RTCC (AT91C_BASE_SYSC + 0xb0) 233 234 #define ATMEL_BASE_SMC (AT91C_BASE_HSMC + 0x700) 235 236 #define AT91C_NUM_PIO 4 237 #define AT91C_NUM_TWI 2 238 239 /* AICREDIR Unlock Key */ 240 #define AICREDIR_KEY 0xB6D81C4D 241 242 /* 243 * Matrix Slaves ID 244 */ 245 /* MATRIX0(H64MX) Matrix Slaves */ 246 /* Bridge from H64MX to AXIMX (Internal ROM, Cryto Library, PKCC RAM) */ 247 #define H64MX_SLAVE_BRIDGE_TO_AXIMX 0 248 #define H64MX_SLAVE_PERI_BRIDGE 1 /* H64MX Peripheral Bridge */ 249 #define H64MX_SLAVE_DDR2_PORT_0 2 /* DDR2 Port0-AESOTF */ 250 #define H64MX_SLAVE_DDR2_PORT_1 3 /* DDR2 Port1 */ 251 #define H64MX_SLAVE_DDR2_PORT_2 4 /* DDR2 Port2 */ 252 #define H64MX_SLAVE_DDR2_PORT_3 5 /* DDR2 Port3 */ 253 #define H64MX_SLAVE_DDR2_PORT_4 6 /* DDR2 Port4 */ 254 #define H64MX_SLAVE_DDR2_PORT_5 7 /* DDR2 Port5 */ 255 #define H64MX_SLAVE_DDR2_PORT_6 8 /* DDR2 Port6 */ 256 #define H64MX_SLAVE_DDR2_PORT_7 9 /* DDR2 Port7 */ 257 #define H64MX_SLAVE_INTERNAL_SRAM 10 /* Internal SRAM 128K */ 258 #define H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K (L2) */ 259 #define H64MX_SLAVE_QSPI0 12 /* QSPI0 */ 260 #define H64MX_SLAVE_QSPI1 13 /* QSPI1 */ 261 #define H64MX_SLAVE_AESB 14 /* AESB */ 262 263 /* MATRIX1(H32MX) Matrix Slaves */ 264 #define H32MX_BRIDGE_TO_H64MX 0 /* Bridge from H32MX to H64MX */ 265 #define H32MX_PERI_BRIDGE_0 1 /* H32MX Peripheral Bridge 0 */ 266 #define H32MX_PERI_BRIDGE_1 2 /* H32MX Peripheral Bridge 1 */ 267 #define H32MX_EXTERNAL_EBI 3 /* External Bus Interface */ 268 #define H32MX_NFC_CMD_REG 3 /* NFC command Register */ 269 #define H32MX_NFC_SRAM 4 /* NFC SRAM */ 270 #define H32MX_USB 5 271 272 #endif /* #ifndef SAMA5D2_H */ 273