1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2017 Timesys Corporation. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <io.h> 30 #include <kernel/boot.h> 31 #include <kernel/tz_ssvce_pl310.h> 32 #include <mm/core_memprot.h> 33 #include <mm/core_mmu.h> 34 #include <sama5d2.h> 35 #include <sam_sfr.h> 36 #include <sam_pl310.h> 37 #include <sm/optee_smc.h> 38 #include <types_ext.h> 39 40 /* L2 Cache Controller (L2CC) */ 41 #define L2CC_DCR_DWB BIT(1) /* Disable Write-back, Force Write-through */ 42 #define L2CC_DCR_DCL BIT(0) /* Disable Cache Linefill */ 43 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 45 46 vaddr_t pl310_base(void) 47 { 48 static void *va; 49 50 if (cpu_mmu_enabled()) { 51 if (!va) 52 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC, 1); 53 return (vaddr_t)va; 54 } 55 return PL310_BASE; 56 } 57 58 void arm_cl2_config(vaddr_t pl310_base) 59 { 60 io_write32(pl310_base + PL310_CTRL, 0); 61 io_write32(sam_sfr_base() + AT91_SFR_L2CC_HRAMC, 0x1); 62 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 63 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 64 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 65 66 /* invalidate all cache ways */ 67 arm_cl2_invbyway(pl310_base); 68 } 69 70 void arm_cl2_enable(vaddr_t pl310_base) 71 { 72 /* Enable PL310 ctrl -> only set lsb bit */ 73 io_write32(pl310_base + PL310_CTRL, 1); 74 } 75 76 #ifdef CFG_PL310_SIP_PROTOCOL 77 TEE_Result pl310_enable(void) 78 { 79 vaddr_t base = pl310_base(); 80 81 arm_cl2_config(base); 82 arm_cl2_enable(base); 83 84 return OPTEE_SMC_RETURN_OK; 85 } 86 87 TEE_Result pl310_disable(void) 88 { 89 EMSG("not implemented"); 90 91 return OPTEE_SMC_RETURN_ENOTAVAIL; 92 } 93 94 TEE_Result pl310_enable_writeback(void) 95 { 96 vaddr_t base = pl310_base(); 97 98 io_write32(base + PL310_DEBUG_CTRL, 0); 99 100 return OPTEE_SMC_RETURN_OK; 101 } 102 103 TEE_Result pl310_disable_writeback(void) 104 { 105 uint32_t val = L2CC_DCR_DWB | L2CC_DCR_DCL; 106 vaddr_t base = pl310_base(); 107 108 io_write32(base + PL310_DEBUG_CTRL, val); 109 110 return OPTEE_SMC_RETURN_OK; 111 } 112 #endif 113