1*f1cf4b79SSumit Garg /* SPDX-License-Identifier: BSD-2-Clause */ 2*f1cf4b79SSumit Garg /* 3*f1cf4b79SSumit Garg * Copyright (c) 2017, Schneider Electric 4*f1cf4b79SSumit Garg * Copyright (c) 2020, Linaro Limited 5*f1cf4b79SSumit Garg */ 6*f1cf4b79SSumit Garg 7*f1cf4b79SSumit Garg #ifndef RZN1_REGAUTH_H 8*f1cf4b79SSumit Garg #define RZN1_REGAUTH_H 9*f1cf4b79SSumit Garg 10*f1cf4b79SSumit Garg struct regauth_t { 11*f1cf4b79SSumit Garg uint32_t paddr; 12*f1cf4b79SSumit Garg uint32_t size; 13*f1cf4b79SSumit Garg uint32_t rmask; 14*f1cf4b79SSumit Garg uint32_t wmask; 15*f1cf4b79SSumit Garg }; 16*f1cf4b79SSumit Garg 17*f1cf4b79SSumit Garg static const struct regauth_t regauth[] = { 18*f1cf4b79SSumit Garg /* OTP */ 19*f1cf4b79SSumit Garg { 0x40007000U, 0x4U, 0x0U, 0x0U }, /* OTPWCTRL */ 20*f1cf4b79SSumit Garg /* System Controller */ 21*f1cf4b79SSumit Garg { 0x4000C064U, 0x4U, 0xFFFFFFFFU, 0xFFFFFFE0U }, /* PWRCTRL_DDRC */ 22*f1cf4b79SSumit Garg { 0x4000C204U, 0x4U, 0x0U, 0x0U }, /* BOOTADDR */ 23*f1cf4b79SSumit Garg /* DDR CTRL */ 24*f1cf4b79SSumit Garg { 0x4000D16CU, 0x3FCU, 0x0U, 0x0U }, /* DDR_CTL 91-346 */ 25*f1cf4b79SSumit Garg { 0x4000E000U, 0x4U, 0xFFFFFFFFU, 0xFFFFFFFEU }, /* UNCCTRL */ 26*f1cf4b79SSumit Garg { 0x4000E004U, 0x4U, 0xFFFFFFFFU, 0xFFFFFFFEU }, /* DLLCTRL */ 27*f1cf4b79SSumit Garg }; 28*f1cf4b79SSumit Garg 29*f1cf4b79SSumit Garg #endif /* RZN1_REGAUTH_H */ 30