xref: /optee_os/core/arch/arm/plat-rockchip/main.c (revision 817466cb476de705a8e3dabe1ef165fe27a18c2f)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  * this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  * this list of conditions and the following disclaimer in the documentation
14  * and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <console.h>
30 #include <drivers/gic.h>
31 #include <drivers/serial8250_uart.h>
32 #include <io.h>
33 #include <kernel/generic_boot.h>
34 #include <kernel/panic.h>
35 #include <kernel/pm_stubs.h>
36 #include <mm/core_memprot.h>
37 #include <platform_config.h>
38 #include <stdint.h>
39 #include <tee/entry_std.h>
40 #include <tee/entry_fast.h>
41 
42 static struct gic_data gic_data;
43 static struct serial8250_uart_data console_data;
44 
45 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_BASE, PERIPH_SIZE);
46 register_phys_mem(MEM_AREA_IO_NSEC, ISRAM_BASE, ISRAM_SIZE);
47 
48 static void main_fiq(void)
49 {
50 	panic();
51 }
52 
53 static const struct thread_handlers handlers = {
54 	.std_smc = tee_entry_std,
55 	.fast_smc = tee_entry_fast,
56 	.nintr = main_fiq,
57 	.cpu_on = pm_do_nothing,
58 	.cpu_off = pm_do_nothing,
59 	.cpu_suspend = pm_do_nothing,
60 	.cpu_resume = pm_do_nothing,
61 	.system_off = pm_do_nothing,
62 	.system_reset = pm_do_nothing,
63 };
64 
65 void main_init_gic(void)
66 {
67 	vaddr_t gicc_base;
68 	vaddr_t gicd_base;
69 
70 	gicc_base = (vaddr_t)phys_to_virt_io(GICC_BASE);
71 	gicd_base = (vaddr_t)phys_to_virt_io(GICD_BASE);
72 
73 	if (!gicc_base || !gicd_base)
74 		panic();
75 
76 	gic_init(&gic_data, gicc_base, gicd_base);
77 	itr_init(&gic_data.chip);
78 }
79 
80 void main_secondary_init_gic(void)
81 {
82 	gic_cpu_init(&gic_data);
83 }
84 
85 const struct thread_handlers *generic_boot_get_handlers(void)
86 {
87 	return &handlers;
88 }
89 
90 void console_init(void)
91 {
92 	serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
93 			     CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
94 	register_serial_console(&console_data.chip);
95 }
96