1 /* 2 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef PLAT_ROCKCHIP_CRU_H 29 #define PLAT_ROCKCHIP_CRU_H 30 31 #include <common.h> 32 #include <platform_config.h> 33 34 #if defined(PLATFORM_FLAVOR_rk322x) 35 36 enum plls_id { 37 APLL_ID, 38 DPLL_ID, 39 CPLL_ID, 40 GPLL_ID, 41 PLL_END, 42 }; 43 44 #define CRU_SOFTRST_CON(i) (0x110 + ((i) * 4)) 45 #define CRU_MODE_CON 0x040 46 #define CRU_GLBRST_CFG_BASE 0x140 47 #define CRU_FSTRST_VAL_BASE 0x1f0 48 #define CRU_SNDRST_VAL_BASE 0x1f4 49 #define CRU_FSTRST_VAL 0xfdb9 50 #define CRU_SNDRST_VAL 0xeca8 51 #define PLLS_SLOW_MODE 0x11030000 52 53 #define CORE_SOFT_RESET(core) SHIFT_U32(0x100010, (core)) 54 #define CORE_SOFT_RELEASE(core) SHIFT_U32(0x100000, (core)) 55 #define CORE_HELD_IN_RESET(core) SHIFT_U32(0x000010, (core)) 56 #define NONBOOT_CORES_SOFT_RESET 0x00e000e0 57 58 #define CRU_CLKGATE_CON_CNT 16 59 #define CRU_CLKSEL_CON(i) (0x044 + ((i) * 4)) 60 #define CRU_CLKGATE_CON(i) (0x0d0 + ((i) * 4)) 61 #define CRU_PLL_CON0(pll) ((pll) * 0x0c + 0x0) 62 #define CRU_PLL_CON1(pll) ((pll) * 0x0c + 0x4) 63 #define CRU_PLL_CON2(pll) ((pll) * 0x0c + 0x8) 64 65 #define PLL_LOCK BIT(10) 66 #define PLL_POWER_UP BITS_WITH_WMASK(0, 1, 13) 67 #define PLL_POWER_DOWN BITS_WITH_WMASK(1, 1, 13) 68 69 #define PLL_MODE_BIT(pll) ((pll) * 4) 70 #define PLL_MODE_MSK(pll) BIT(PLL_MODE_BIT(pll)) 71 #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll)) 72 #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll)) 73 #endif 74 75 #endif 76