1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLAT_ROCKCHIP_COMMON_H 30 #define PLAT_ROCKCHIP_COMMON_H 31 32 /* For SMP cpu bootup, they are common for rockchip platforms */ 33 #define LOCK_TAG 0xDEADBEAF 34 #define LOCK_ADDR_OFFSET 4 35 #define BOOT_ADDR_OFFSET 8 36 37 /* 38 * Some register has write-mask bits, it means if you want to set the bits, 39 * you need set the write-mask bits at the same time, the write-mask bits is 40 * in high 16-bits. The following macro definition helps you access register 41 * efficiently. 42 */ 43 #define REG_MSK_SHIFT 16 44 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 45 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 46 #define BITS_WMSK(msk, shift) SHIFT_U32(msk, (shift) + REG_MSK_SHIFT) 47 #define BITS_WITH_WMASK(bits, msk, shift) \ 48 (SHIFT_U32(bits, shift) | BITS_WMSK(msk, shift)) 49 50 #endif 51