1PLATFORM_FLAVOR ?= salvator_h3 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_PM_STUBS,y) 6$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 7$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 8$(call force,CFG_SCIF,y) 9$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) 10$(call force,CFG_CORE_ARM64_PA_BITS,36) 11 12# Disable core ASLR for two reasons: 13# 1. There is no source for ALSR seed, as Rcar platform 14# does not provide DTB to OP-TEE. Also, there is no 15# publically available documentation on integrated 16# hardware RNG, so we can't use it either. 17# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR. 18$(call force,CFG_CORE_ASLR,n) 19 20ifeq ($(PLATFORM_FLAVOR),salvator_h3) 21$(call force,CFG_TEE_CORE_NB_CORE,8) 22endif 23ifeq ($(PLATFORM_FLAVOR),salvator_h3_4x2g) 24$(call force,CFG_TEE_CORE_NB_CORE,8) 25endif 26ifeq ($(PLATFORM_FLAVOR),salvator_m3) 27$(call force,CFG_TEE_CORE_NB_CORE,6) 28# This somewhat abuses implementation of get_core_pos_mpidr() 29# M3 have 6 cores, but internaly they have ids 0, 1, 4, 5, 6, 7. 30# By setting CFG_CORE_CLUSTER_SHIFT to 1, get_core_pos_mpidr() 31# will produce correct numbers: 0, 1, 2, 3, 4, 5 32$(call force,CFG_CORE_CLUSTER_SHIFT,1) 33endif 34 35CFG_TZDRAM_START ?= 0x44100000 36CFG_TZDRAM_SIZE ?= 0x03D00000 37CFG_TEE_RAM_VA_SIZE ?= 0x100000 38ifeq ($(CFG_ARM64_core),y) 39$(call force,CFG_WITH_LPAE,y) 40supported-ta-targets = ta_arm64 41else 42$(call force,CFG_ARM32_core,y) 43endif 44