1PLATFORM_FLAVOR ?= salvator_h3 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 6$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 7$(call force,CFG_SCIF,y) 8$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) 9$(call force,CFG_CORE_ARM64_PA_BITS,36) 10 11# Disable core ASLR for two reasons: 12# 1. There is no source for ALSR seed, as Rcar platform 13# does not provide DTB to OP-TEE. Also, there is no 14# publically available documentation on integrated 15# hardware RNG, so we can't use it either. 16# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR. 17$(call force,CFG_CORE_ASLR,n) 18 19ifeq ($(PLATFORM_FLAVOR),salvator_h3) 20$(call force,CFG_TEE_CORE_NB_CORE,8) 21endif 22ifeq ($(PLATFORM_FLAVOR),salvator_h3_4x2g) 23$(call force,CFG_TEE_CORE_NB_CORE,8) 24endif 25ifeq ($(PLATFORM_FLAVOR),salvator_m3) 26$(call force,CFG_TEE_CORE_NB_CORE,6) 27# This somewhat abuses implementation of get_core_pos_mpidr() 28# M3 have 6 cores, but internaly they have ids 0, 1, 4, 5, 6, 7. 29# By setting CFG_CORE_CLUSTER_SHIFT to 1, get_core_pos_mpidr() 30# will produce correct numbers: 0, 1, 2, 3, 4, 5 31$(call force,CFG_CORE_CLUSTER_SHIFT,1) 32endif 33 34CFG_TZDRAM_START ?= 0x44100000 35CFG_TZDRAM_SIZE ?= 0x03D00000 36CFG_TEE_RAM_VA_SIZE ?= 0x100000 37ifeq ($(CFG_ARM64_core),y) 38$(call force,CFG_WITH_LPAE,y) 39supported-ta-targets = ta_arm64 40else 41$(call force,CFG_ARM32_core,y) 42endif 43 44CFG_DT ?= y 45