1PLATFORM_FLAVOR ?= salvator_h3 2 3include core/arch/arm/cpu/cortex-armv8-0.mk 4 5$(call force,CFG_GENERIC_BOOT,y) 6$(call force,CFG_PM_STUBS,y) 7$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 8$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 9$(call force,CFG_SCIF,y) 10$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) 11$(call force,CFG_CORE_ARM64_PA_BITS,36) 12 13# Disable core ASLR for two reasons: 14# 1. There is no source for ALSR seed, as Rcar platform 15# does not provide DTB to OP-TEE. Also, there is no 16# publically available documentation on integrated 17# hardware RNG, so we can't use it either. 18# 2. OP-TEE crashes during boot with enabled CFG_CORE_ASLR. 19$(call force,CFG_CORE_ASLR,n) 20 21ifeq ($(PLATFORM_FLAVOR),salvator_h3) 22$(call force,CFG_TEE_CORE_NB_CORE,8) 23endif 24ifeq ($(PLATFORM_FLAVOR),salvator_h3_4x2g) 25$(call force,CFG_TEE_CORE_NB_CORE,8) 26endif 27ifeq ($(PLATFORM_FLAVOR),salvator_m3) 28$(call force,CFG_TEE_CORE_NB_CORE,6) 29# This somewhat abuses implementation of get_core_pos_mpidr() 30# M3 have 6 cores, but internaly they have ids 0, 1, 4, 5, 6, 7. 31# By setting CFG_CORE_CLUSTER_SHIFT to 1, get_core_pos_mpidr() 32# will produce correct numbers: 0, 1, 2, 3, 4, 5 33$(call force,CFG_CORE_CLUSTER_SHIFT,1) 34endif 35 36CFG_TZDRAM_START ?= 0x44100000 37CFG_TZDRAM_SIZE ?= 0x03D00000 38CFG_TEE_RAM_VA_SIZE ?= 0x100000 39ifeq ($(CFG_ARM64_core),y) 40$(call force,CFG_WITH_LPAE,y) 41supported-ta-targets = ta_arm64 42else 43$(call force,CFG_ARM32_core,y) 44endif 45 46CFG_WITH_STACK_CANARIES ?= y 47