1/* 2 * Copyright (c) 2016, Wind River Systems. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28/* 29 * Entry points for the A9 inits, A9 revision specific or not. 30 * It is assume no stack is available when these routines are called. 31 * It is assume each routine is called with return address in LR 32 * and with ARM registers R0, R1, R2, R3 being scratchable. 33 */ 34 35#include <arm32.h> 36#include <arm32_macros.S> 37#include <asm.S> 38#include <kernel/unwind.h> 39#include <platform_config.h> 40 41.section .text 42.balign 4 43.code 32 44 45/* 46 * platform early configuration 47 * 48 * Use scratables registers R0-R3. 49 * No stack usage. 50 * LR store return address. 51 * Trap CPU in case of error. 52 */ 53FUNC plat_cpu_reset_early , : 54UNWIND( .fnstart) 55 56 /* 57 * Disallow NSec to mask FIQ [bit4: FW=0] 58 * Allow NSec to manage Imprecise Abort [bit5: AW=1] 59 * Imprecise Abort trapped to Abort Mode [bit3: EA=0] 60 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] 61 * IRQ always trapped to IRQ Mode [bit1: IRQ=0] 62 * Secure World [bit0: NS=0] 63 */ 64 mov r0, #SCR_AW 65 write_scr r0 /* write Secure Configuration Register */ 66 67 /* 68 * Mandated HW config loaded 69 * 70 * SCTLR = 0x00000000 71 * 72 * ACTRL = 0x00000040 73 * - core NOT booted in full SMP (FW bit0=0) 74 * 75 * NSACR = 0x00000C00 76 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 77 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 78 */ 79 mov_imm r0, 0x00000000 80 write_sctlr r0 81 82 mov_imm r0, 0x00000040 83 write_actlr r0 84 85 mov_imm r0, 0x00000C00 86 write_nsacr r0 87 88 mov pc, lr 89UNWIND( .fnend) 90END_FUNC plat_cpu_reset_early 91