1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2016, Wind River Systems. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * Entry points for the A9 inits, A9 revision specific or not. 31 * It is assume no stack is available when these routines are called. 32 * It is assume each routine is called with return address in LR 33 * and with ARM registers R0, R1, R2, R3 being scratchable. 34 */ 35 36#include <arm32.h> 37#include <arm32_macros.S> 38#include <asm.S> 39#include <kernel/unwind.h> 40#include <platform_config.h> 41 42.section .text 43.balign 4 44.code 32 45 46/* 47 * platform early configuration 48 * 49 * Use scratables registers R0-R3. 50 * No stack usage. 51 * LR store return address. 52 * Trap CPU in case of error. 53 */ 54FUNC plat_cpu_reset_early , : 55UNWIND( .fnstart) 56 57 /* 58 * Disallow NSec to mask FIQ [bit4: FW=0] 59 * Allow NSec to manage Imprecise Abort [bit5: AW=1] 60 * Imprecise Abort trapped to Abort Mode [bit3: EA=0] 61 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] 62 * IRQ always trapped to IRQ Mode [bit1: IRQ=0] 63 * Secure World [bit0: NS=0] 64 */ 65 mov r0, #SCR_AW 66 write_scr r0 /* write Secure Configuration Register */ 67 68 /* 69 * Mandated HW config loaded 70 * 71 * SCTLR = 0x00000000 72 * 73 * ACTRL = 0x00000040 74 * - core NOT booted in full SMP (FW bit0=0) 75 * 76 * NSACR = 0x00000C00 77 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 78 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 79 */ 80 mov_imm r0, 0x00000000 81 write_sctlr r0 82 83 mov_imm r0, 0x00000040 84 write_actlr r0 85 86 mov_imm r0, 0x00000C00 87 write_nsacr r0 88 89 mov pc, lr 90UNWIND( .fnend) 91END_FUNC plat_cpu_reset_early 92