1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #include <drivers/ns16550.h> 36 #include <io.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <kernel/thread.h> 42 #include <kernel/tz_ssvce_def.h> 43 #include <mm/core_memprot.h> 44 #include <sm/optee_smc.h> 45 #include <tee/entry_fast.h> 46 #include <tee/entry_std.h> 47 #include <kernel/tee_common_otp.h> 48 #include <mm/core_mmu.h> 49 50 static void main_fiq(void); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = tee_entry_fast, 55 .nintr = main_fiq, 56 #if defined(CFG_WITH_ARM_TRUSTED_FW) 57 .cpu_on = cpu_on_handler, 58 .cpu_off = pm_do_nothing, 59 .cpu_suspend = pm_do_nothing, 60 .cpu_resume = pm_do_nothing, 61 .system_off = pm_do_nothing, 62 .system_reset = pm_do_nothing, 63 #else 64 .cpu_on = pm_panic, 65 .cpu_off = pm_panic, 66 .cpu_suspend = pm_panic, 67 .cpu_resume = pm_panic, 68 .system_off = pm_panic, 69 .system_reset = pm_panic, 70 #endif 71 }; 72 73 static struct gic_data gic_data; 74 static struct ns16550_data console_data; 75 76 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 77 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 78 79 const struct thread_handlers *generic_boot_get_handlers(void) 80 { 81 return &handlers; 82 } 83 84 static void main_fiq(void) 85 { 86 panic(); 87 } 88 89 #ifdef CFG_ARM32_core 90 void plat_cpu_reset_late(void) 91 { 92 static uint32_t cntfrq; 93 vaddr_t addr; 94 95 if (!get_core_pos()) { 96 /* read cnt freq */ 97 cntfrq = read_cntfrq(); 98 99 #if defined(CFG_BOOT_SECONDARY_REQUEST) 100 /* set secondary entry address */ 101 write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR), 102 DCFG_BASE + DCFG_SCRATCHRW1); 103 104 /* release secondary cores */ 105 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 106 DCFG_BASE + DCFG_CCSR_BRR); 107 dsb(); 108 sev(); 109 #endif 110 111 /* configure CSU */ 112 113 /* first grant all peripherals */ 114 for (addr = CSU_BASE + CSU_CSL_START; 115 addr != CSU_BASE + CSU_CSL_END; 116 addr += 4) 117 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 118 119 /* restrict key preipherals from NS */ 120 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 121 CSU_BASE + CSU_CSL30); 122 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 123 CSU_BASE + CSU_CSL37); 124 125 /* lock the settings */ 126 for (addr = CSU_BASE + CSU_CSL_START; 127 addr != CSU_BASE + CSU_CSL_END; 128 addr += 4) 129 write32(read32(addr) | 130 __compiler_bswap32(CSU_SETTING_LOCK), 131 addr); 132 } else { 133 /* program the cntfrq, the cntfrq is banked for each core */ 134 write_cntfrq(cntfrq); 135 } 136 } 137 #endif 138 139 void console_init(void) 140 { 141 ns16550_init(&console_data, CONSOLE_UART_BASE); 142 register_serial_console(&console_data.chip); 143 } 144 145 void main_init_gic(void) 146 { 147 vaddr_t gicc_base; 148 vaddr_t gicd_base; 149 150 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 151 MEM_AREA_IO_SEC); 152 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 153 MEM_AREA_IO_SEC); 154 155 if (!gicc_base || !gicd_base) 156 panic(); 157 158 /* Initialize GIC */ 159 gic_init(&gic_data, gicc_base, gicd_base); 160 itr_init(&gic_data.chip); 161 } 162 163 void main_secondary_init_gic(void) 164 { 165 gic_cpu_init(&gic_data); 166 } 167 168 #ifdef CFG_HW_UNQ_KEY_REQUEST 169 170 #include <types_ext.h> 171 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 172 173 /* 174 * Issued when requesting to Secure Storage Key for secure storage. 175 * 176 * SiP Service Calls 177 * 178 * Register usage: 179 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 180 */ 181 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 182 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 183 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 184 OPTEE_SMC_OWNER_SIP, \ 185 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 186 187 void tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 188 { 189 int ret = 0; 190 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 191 192 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 193 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 194 195 if (ret < 0) 196 EMSG("\nH/W Unique key is not fetched from the platform."); 197 else 198 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 199 } 200 #endif 201