1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/ns16550.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <kernel/thread.h> 40 #include <kernel/tz_ssvce_def.h> 41 #include <mm/core_memprot.h> 42 #include <sm/optee_smc.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 46 static void main_fiq(void); 47 48 static const struct thread_handlers handlers = { 49 .std_smc = tee_entry_std, 50 .fast_smc = tee_entry_fast, 51 .nintr = main_fiq, 52 .cpu_on = pm_panic, 53 .cpu_off = pm_panic, 54 .cpu_suspend = pm_panic, 55 .cpu_resume = pm_panic, 56 .system_off = pm_panic, 57 .system_reset = pm_panic, 58 }; 59 60 static struct gic_data gic_data; 61 static struct ns16550_data console_data; 62 63 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 64 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 65 66 const struct thread_handlers *generic_boot_get_handlers(void) 67 { 68 return &handlers; 69 } 70 71 static void main_fiq(void) 72 { 73 panic(); 74 } 75 76 void plat_cpu_reset_late(void) 77 { 78 static uint32_t cntfrq; 79 vaddr_t addr; 80 81 if (!get_core_pos()) { 82 /* read cnt freq */ 83 cntfrq = read_cntfrq(); 84 85 #if defined(CFG_BOOT_SECONDARY_REQUEST) 86 /* set secondary entry address */ 87 write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR), 88 DCFG_BASE + DCFG_SCRATCHRW1); 89 90 /* release secondary cores */ 91 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 92 DCFG_BASE + DCFG_CCSR_BRR); 93 dsb(); 94 sev(); 95 #endif 96 97 /* configure CSU */ 98 99 /* first grant all peripherals */ 100 for (addr = CSU_BASE + CSU_CSL_START; 101 addr != CSU_BASE + CSU_CSL_END; 102 addr += 4) 103 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 104 105 /* restrict key preipherals from NS */ 106 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 107 CSU_BASE + CSU_CSL30); 108 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 109 CSU_BASE + CSU_CSL37); 110 111 /* lock the settings */ 112 for (addr = CSU_BASE + CSU_CSL_START; 113 addr != CSU_BASE + CSU_CSL_END; 114 addr += 4) 115 write32(read32(addr) | 116 __compiler_bswap32(CSU_SETTING_LOCK), 117 addr); 118 } else { 119 /* program the cntfrq, the cntfrq is banked for each core */ 120 write_cntfrq(cntfrq); 121 } 122 } 123 124 void console_init(void) 125 { 126 ns16550_init(&console_data, CONSOLE_UART_BASE); 127 register_serial_console(&console_data.chip); 128 } 129 130 void main_init_gic(void) 131 { 132 vaddr_t gicc_base; 133 vaddr_t gicd_base; 134 135 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 136 MEM_AREA_IO_SEC); 137 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 138 MEM_AREA_IO_SEC); 139 140 if (!gicc_base || !gicd_base) 141 panic(); 142 143 /* Initialize GIC */ 144 gic_init(&gic_data, gicc_base, gicd_base); 145 itr_init(&gic_data.chip); 146 } 147 148 void main_secondary_init_gic(void) 149 { 150 gic_cpu_init(&gic_data); 151 } 152