1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #ifdef CFG_PL011 36 #include <drivers/pl011.h> 37 #else 38 #include <drivers/ns16550.h> 39 #endif 40 #include <io.h> 41 #include <kernel/boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/thread.h> 45 #include <kernel/tz_ssvce_def.h> 46 #include <mm/core_memprot.h> 47 #include <sm/optee_smc.h> 48 #include <kernel/tee_common_otp.h> 49 #include <mm/core_mmu.h> 50 51 static struct gic_data gic_data; 52 #ifdef CFG_PL011 53 static struct pl011_data console_data; 54 #else 55 static struct ns16550_data console_data; 56 #endif 57 58 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 59 CORE_MMU_PGDIR_SIZE); 60 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 61 62 #ifdef CFG_ARM32_core 63 void plat_primary_init_early(void) 64 { 65 vaddr_t addr; 66 67 #if defined(CFG_BOOT_SECONDARY_REQUEST) 68 /* set secondary entry address */ 69 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, 70 __compiler_bswap32(TEE_LOAD_ADDR)); 71 72 /* release secondary cores */ 73 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, 74 __compiler_bswap32(0x1 << 1)); 75 dsb(); 76 sev(); 77 #endif 78 79 /* configure CSU */ 80 81 /* first grant all peripherals */ 82 for (addr = CSU_BASE + CSU_CSL_START; 83 addr != CSU_BASE + CSU_CSL_END; 84 addr += 4) 85 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); 86 87 /* restrict key preipherals from NS */ 88 io_write32(CSU_BASE + CSU_CSL30, 89 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 90 io_write32(CSU_BASE + CSU_CSL37, 91 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 92 93 /* lock the settings */ 94 for (addr = CSU_BASE + CSU_CSL_START; 95 addr != CSU_BASE + CSU_CSL_END; 96 addr += 4) 97 io_setbits32(addr, 98 __compiler_bswap32(CSU_SETTING_LOCK)); 99 } 100 #endif 101 102 void console_init(void) 103 { 104 #ifdef CFG_PL011 105 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 106 CONSOLE_BAUDRATE); 107 #else 108 ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U8, 0); 109 #endif 110 register_serial_console(&console_data.chip); 111 } 112 113 void main_init_gic(void) 114 { 115 vaddr_t gicc_base; 116 vaddr_t gicd_base; 117 118 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 119 MEM_AREA_IO_SEC); 120 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 121 MEM_AREA_IO_SEC); 122 123 if (!gicc_base || !gicd_base) 124 panic(); 125 126 /* Initialize GIC */ 127 gic_init(&gic_data, gicc_base, gicd_base); 128 itr_init(&gic_data.chip); 129 } 130 131 void main_secondary_init_gic(void) 132 { 133 gic_cpu_init(&gic_data); 134 } 135 136 #ifdef CFG_HW_UNQ_KEY_REQUEST 137 138 #include <types_ext.h> 139 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 140 141 /* 142 * Issued when requesting to Secure Storage Key for secure storage. 143 * 144 * SiP Service Calls 145 * 146 * Register usage: 147 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 148 */ 149 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 150 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 151 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 152 OPTEE_SMC_OWNER_SIP, \ 153 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 154 155 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 156 { 157 TEE_Result res; 158 int ret = 0; 159 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 160 161 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 162 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 163 164 if (ret < 0) { 165 EMSG("\nH/W Unique key is not fetched from the platform."); 166 res = TEE_ERROR_SECURITY; 167 } else { 168 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 169 res = TEE_SUCCESS; 170 } 171 172 return res; 173 } 174 #endif 175