1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <arm.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/ns16550.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <kernel/thread.h> 40 #include <kernel/tz_ssvce_def.h> 41 #include <mm/core_memprot.h> 42 #include <sm/optee_smc.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 46 static void main_fiq(void); 47 48 static const struct thread_handlers handlers = { 49 .std_smc = tee_entry_std, 50 .fast_smc = tee_entry_fast, 51 .nintr = main_fiq, 52 #if defined(CFG_WITH_ARM_TRUSTED_FW) 53 .cpu_on = cpu_on_handler, 54 .cpu_off = pm_do_nothing, 55 .cpu_suspend = pm_do_nothing, 56 .cpu_resume = pm_do_nothing, 57 .system_off = pm_do_nothing, 58 .system_reset = pm_do_nothing, 59 #else 60 .cpu_on = pm_panic, 61 .cpu_off = pm_panic, 62 .cpu_suspend = pm_panic, 63 .cpu_resume = pm_panic, 64 .system_off = pm_panic, 65 .system_reset = pm_panic, 66 #endif 67 }; 68 69 static struct gic_data gic_data; 70 static struct ns16550_data console_data; 71 72 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 73 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 74 75 const struct thread_handlers *generic_boot_get_handlers(void) 76 { 77 return &handlers; 78 } 79 80 static void main_fiq(void) 81 { 82 panic(); 83 } 84 85 #ifdef CFG_ARM32_core 86 void plat_cpu_reset_late(void) 87 { 88 static uint32_t cntfrq; 89 vaddr_t addr; 90 91 if (!get_core_pos()) { 92 /* read cnt freq */ 93 cntfrq = read_cntfrq(); 94 95 #if defined(CFG_BOOT_SECONDARY_REQUEST) 96 /* set secondary entry address */ 97 write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR), 98 DCFG_BASE + DCFG_SCRATCHRW1); 99 100 /* release secondary cores */ 101 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 102 DCFG_BASE + DCFG_CCSR_BRR); 103 dsb(); 104 sev(); 105 #endif 106 107 /* configure CSU */ 108 109 /* first grant all peripherals */ 110 for (addr = CSU_BASE + CSU_CSL_START; 111 addr != CSU_BASE + CSU_CSL_END; 112 addr += 4) 113 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 114 115 /* restrict key preipherals from NS */ 116 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 117 CSU_BASE + CSU_CSL30); 118 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 119 CSU_BASE + CSU_CSL37); 120 121 /* lock the settings */ 122 for (addr = CSU_BASE + CSU_CSL_START; 123 addr != CSU_BASE + CSU_CSL_END; 124 addr += 4) 125 write32(read32(addr) | 126 __compiler_bswap32(CSU_SETTING_LOCK), 127 addr); 128 } else { 129 /* program the cntfrq, the cntfrq is banked for each core */ 130 write_cntfrq(cntfrq); 131 } 132 } 133 #endif 134 135 void console_init(void) 136 { 137 ns16550_init(&console_data, CONSOLE_UART_BASE); 138 register_serial_console(&console_data.chip); 139 } 140 141 void main_init_gic(void) 142 { 143 vaddr_t gicc_base; 144 vaddr_t gicd_base; 145 146 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 147 MEM_AREA_IO_SEC); 148 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 149 MEM_AREA_IO_SEC); 150 151 if (!gicc_base || !gicd_base) 152 panic(); 153 154 /* Initialize GIC */ 155 gic_init(&gic_data, gicc_base, gicd_base); 156 itr_init(&gic_data.chip); 157 } 158 159 void main_secondary_init_gic(void) 160 { 161 gic_cpu_init(&gic_data); 162 } 163