1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <platform_config.h> 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/ns16550.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <kernel/thread.h> 40 #include <kernel/tz_ssvce_def.h> 41 #include <mm/core_memprot.h> 42 #include <sm/optee_smc.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 46 static void main_fiq(void); 47 48 static const struct thread_handlers handlers = { 49 .std_smc = tee_entry_std, 50 .fast_smc = tee_entry_fast, 51 .nintr = main_fiq, 52 .cpu_on = pm_panic, 53 .cpu_off = pm_panic, 54 .cpu_suspend = pm_panic, 55 .cpu_resume = pm_panic, 56 .system_off = pm_panic, 57 .system_reset = pm_panic, 58 }; 59 60 static struct gic_data gic_data; 61 62 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 63 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 64 65 const struct thread_handlers *generic_boot_get_handlers(void) 66 { 67 return &handlers; 68 } 69 70 static void main_fiq(void) 71 { 72 panic(); 73 } 74 75 void plat_cpu_reset_late(void) 76 { 77 static uint32_t cntfrq __early_bss; 78 vaddr_t addr; 79 80 if (!get_core_pos()) { 81 /* read cnt freq */ 82 cntfrq = read_cntfrq(); 83 84 #if defined(CFG_BOOT_SECONDARY_REQUEST) 85 /* set secondary entry address */ 86 write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR), 87 DCFG_BASE + DCFG_SCRATCHRW1); 88 89 /* release secondary cores */ 90 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 91 DCFG_BASE + DCFG_CCSR_BRR); 92 dsb(); 93 sev(); 94 #endif 95 96 /* configure CSU */ 97 98 /* first grant all peripherals */ 99 for (addr = CSU_BASE + CSU_CSL_START; 100 addr != CSU_BASE + CSU_CSL_END; 101 addr += 4) 102 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 103 104 /* restrict key preipherals from NS */ 105 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 106 CSU_BASE + CSU_CSL30); 107 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 108 CSU_BASE + CSU_CSL37); 109 110 /* lock the settings */ 111 for (addr = CSU_BASE + CSU_CSL_START; 112 addr != CSU_BASE + CSU_CSL_END; 113 addr += 4) 114 write32(read32(addr) | 115 __compiler_bswap32(CSU_SETTING_LOCK), 116 addr); 117 } else { 118 /* program the cntfrq, the cntfrq is banked for each core */ 119 write_cntfrq(cntfrq); 120 } 121 } 122 123 static vaddr_t console_base(void) 124 { 125 static void *va __early_bss; 126 127 if (cpu_mmu_enabled()) { 128 if (!va) 129 va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_NSEC); 130 return (vaddr_t)va; 131 } 132 return CONSOLE_UART_BASE; 133 } 134 135 void console_init(void) 136 { 137 /* 138 * Do nothing, uart driver shared with normal world, 139 * everything for uart driver intialization is done in bootloader. 140 */ 141 } 142 143 void console_putc(int ch) 144 { 145 vaddr_t base = console_base(); 146 147 if (ch == '\n') 148 ns16550_putc('\r', base); 149 ns16550_putc(ch, base); 150 } 151 152 void console_flush(void) 153 { 154 ns16550_flush(console_base()); 155 } 156 157 void main_init_gic(void) 158 { 159 vaddr_t gicc_base; 160 vaddr_t gicd_base; 161 162 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 163 MEM_AREA_IO_SEC); 164 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 165 MEM_AREA_IO_SEC); 166 167 if (!gicc_base || !gicd_base) 168 panic(); 169 170 /* Initialize GIC */ 171 gic_init(&gic_data, gicc_base, gicd_base); 172 itr_init(&gic_data.chip); 173 } 174 175 void main_secondary_init_gic(void) 176 { 177 gic_cpu_init(&gic_data); 178 } 179