1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #ifdef CFG_PL011 36 #include <drivers/pl011.h> 37 #else 38 #include <drivers/ns16550.h> 39 #endif 40 #include <io.h> 41 #include <kernel/generic_boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/pm_stubs.h> 45 #include <kernel/thread.h> 46 #include <kernel/tz_ssvce_def.h> 47 #include <mm/core_memprot.h> 48 #include <sm/optee_smc.h> 49 #include <tee/entry_fast.h> 50 #include <tee/entry_std.h> 51 #include <kernel/tee_common_otp.h> 52 #include <mm/core_mmu.h> 53 54 static void main_fiq(void); 55 56 static const struct thread_handlers handlers = { 57 .std_smc = tee_entry_std, 58 .fast_smc = tee_entry_fast, 59 .nintr = main_fiq, 60 #if defined(CFG_WITH_ARM_TRUSTED_FW) 61 .cpu_on = cpu_on_handler, 62 .cpu_off = pm_do_nothing, 63 .cpu_suspend = pm_do_nothing, 64 .cpu_resume = pm_do_nothing, 65 .system_off = pm_do_nothing, 66 .system_reset = pm_do_nothing, 67 #else 68 .cpu_on = pm_panic, 69 .cpu_off = pm_panic, 70 .cpu_suspend = pm_panic, 71 .cpu_resume = pm_panic, 72 .system_off = pm_panic, 73 .system_reset = pm_panic, 74 #endif 75 }; 76 77 static struct gic_data gic_data; 78 #ifdef CFG_PL011 79 static struct pl011_data console_data; 80 #else 81 static struct ns16550_data console_data; 82 #endif 83 84 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 85 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 86 87 const struct thread_handlers *generic_boot_get_handlers(void) 88 { 89 return &handlers; 90 } 91 92 static void main_fiq(void) 93 { 94 panic(); 95 } 96 97 #ifdef CFG_ARM32_core 98 void plat_cpu_reset_late(void) 99 { 100 vaddr_t addr; 101 102 if (!get_core_pos()) { 103 #if defined(CFG_BOOT_SECONDARY_REQUEST) 104 /* set secondary entry address */ 105 write32(__compiler_bswap32(TEE_LOAD_ADDR), 106 DCFG_BASE + DCFG_SCRATCHRW1); 107 108 /* release secondary cores */ 109 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 110 DCFG_BASE + DCFG_CCSR_BRR); 111 dsb(); 112 sev(); 113 #endif 114 115 /* configure CSU */ 116 117 /* first grant all peripherals */ 118 for (addr = CSU_BASE + CSU_CSL_START; 119 addr != CSU_BASE + CSU_CSL_END; 120 addr += 4) 121 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 122 123 /* restrict key preipherals from NS */ 124 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 125 CSU_BASE + CSU_CSL30); 126 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 127 CSU_BASE + CSU_CSL37); 128 129 /* lock the settings */ 130 for (addr = CSU_BASE + CSU_CSL_START; 131 addr != CSU_BASE + CSU_CSL_END; 132 addr += 4) 133 write32(read32(addr) | 134 __compiler_bswap32(CSU_SETTING_LOCK), 135 addr); 136 } 137 } 138 #endif 139 140 void console_init(void) 141 { 142 #ifdef CFG_PL011 143 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 144 CONSOLE_BAUDRATE); 145 #else 146 ns16550_init(&console_data, CONSOLE_UART_BASE); 147 #endif 148 register_serial_console(&console_data.chip); 149 } 150 151 void main_init_gic(void) 152 { 153 vaddr_t gicc_base; 154 vaddr_t gicd_base; 155 156 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 157 MEM_AREA_IO_SEC); 158 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 159 MEM_AREA_IO_SEC); 160 161 if (!gicc_base || !gicd_base) 162 panic(); 163 164 /* Initialize GIC */ 165 gic_init(&gic_data, gicc_base, gicd_base); 166 itr_init(&gic_data.chip); 167 } 168 169 void main_secondary_init_gic(void) 170 { 171 gic_cpu_init(&gic_data); 172 } 173 174 #ifdef CFG_HW_UNQ_KEY_REQUEST 175 176 #include <types_ext.h> 177 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 178 179 /* 180 * Issued when requesting to Secure Storage Key for secure storage. 181 * 182 * SiP Service Calls 183 * 184 * Register usage: 185 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 186 */ 187 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 188 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 189 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 190 OPTEE_SMC_OWNER_SIP, \ 191 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 192 193 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 194 { 195 TEE_Result res; 196 int ret = 0; 197 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 198 199 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 200 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 201 202 if (ret < 0) { 203 EMSG("\nH/W Unique key is not fetched from the platform."); 204 res = TEE_ERROR_SECURITY; 205 } else { 206 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 207 res = TEE_SUCCESS; 208 } 209 210 return res; 211 } 212 #endif 213