1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #ifdef CFG_PL011 36 #include <drivers/pl011.h> 37 #else 38 #include <drivers/ns16550.h> 39 #endif 40 #include <io.h> 41 #include <kernel/generic_boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/pm_stubs.h> 45 #include <kernel/thread.h> 46 #include <kernel/tz_ssvce_def.h> 47 #include <mm/core_memprot.h> 48 #include <sm/optee_smc.h> 49 #include <tee/entry_fast.h> 50 #include <tee/entry_std.h> 51 #include <kernel/tee_common_otp.h> 52 #include <mm/core_mmu.h> 53 54 static const struct thread_handlers handlers = { 55 #if defined(CFG_WITH_ARM_TRUSTED_FW) 56 .cpu_on = cpu_on_handler, 57 .cpu_off = pm_do_nothing, 58 .cpu_suspend = pm_do_nothing, 59 .cpu_resume = pm_do_nothing, 60 .system_off = pm_do_nothing, 61 .system_reset = pm_do_nothing, 62 #else 63 .cpu_on = pm_panic, 64 .cpu_off = pm_panic, 65 .cpu_suspend = pm_panic, 66 .cpu_resume = pm_panic, 67 .system_off = pm_panic, 68 .system_reset = pm_panic, 69 #endif 70 }; 71 72 static struct gic_data gic_data; 73 #ifdef CFG_PL011 74 static struct pl011_data console_data; 75 #else 76 static struct ns16550_data console_data; 77 #endif 78 79 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 80 CORE_MMU_PGDIR_SIZE); 81 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 82 83 const struct thread_handlers *generic_boot_get_handlers(void) 84 { 85 return &handlers; 86 } 87 88 #ifdef CFG_ARM32_core 89 void plat_cpu_reset_late(void) 90 { 91 vaddr_t addr; 92 93 if (!get_core_pos()) { 94 #if defined(CFG_BOOT_SECONDARY_REQUEST) 95 /* set secondary entry address */ 96 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, 97 __compiler_bswap32(TEE_LOAD_ADDR)); 98 99 /* release secondary cores */ 100 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, 101 __compiler_bswap32(0x1 << 1)); 102 dsb(); 103 sev(); 104 #endif 105 106 /* configure CSU */ 107 108 /* first grant all peripherals */ 109 for (addr = CSU_BASE + CSU_CSL_START; 110 addr != CSU_BASE + CSU_CSL_END; 111 addr += 4) 112 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); 113 114 /* restrict key preipherals from NS */ 115 io_write32(CSU_BASE + CSU_CSL30, 116 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 117 io_write32(CSU_BASE + CSU_CSL37, 118 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 119 120 /* lock the settings */ 121 for (addr = CSU_BASE + CSU_CSL_START; 122 addr != CSU_BASE + CSU_CSL_END; 123 addr += 4) 124 io_setbits32(addr, 125 __compiler_bswap32(CSU_SETTING_LOCK)); 126 } 127 } 128 #endif 129 130 void console_init(void) 131 { 132 #ifdef CFG_PL011 133 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 134 CONSOLE_BAUDRATE); 135 #else 136 ns16550_init(&console_data, CONSOLE_UART_BASE); 137 #endif 138 register_serial_console(&console_data.chip); 139 } 140 141 void main_init_gic(void) 142 { 143 vaddr_t gicc_base; 144 vaddr_t gicd_base; 145 146 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 147 MEM_AREA_IO_SEC); 148 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 149 MEM_AREA_IO_SEC); 150 151 if (!gicc_base || !gicd_base) 152 panic(); 153 154 /* Initialize GIC */ 155 gic_init(&gic_data, gicc_base, gicd_base); 156 itr_init(&gic_data.chip); 157 } 158 159 void main_secondary_init_gic(void) 160 { 161 gic_cpu_init(&gic_data); 162 } 163 164 #ifdef CFG_HW_UNQ_KEY_REQUEST 165 166 #include <types_ext.h> 167 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 168 169 /* 170 * Issued when requesting to Secure Storage Key for secure storage. 171 * 172 * SiP Service Calls 173 * 174 * Register usage: 175 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 176 */ 177 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 178 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 179 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 180 OPTEE_SMC_OWNER_SIP, \ 181 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 182 183 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 184 { 185 TEE_Result res; 186 int ret = 0; 187 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 188 189 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 190 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 191 192 if (ret < 0) { 193 EMSG("\nH/W Unique key is not fetched from the platform."); 194 res = TEE_ERROR_SECURITY; 195 } else { 196 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 197 res = TEE_SUCCESS; 198 } 199 200 return res; 201 } 202 #endif 203