1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 12include core/arch/arm/cpu/cortex-a7.mk 13$(call force,CFG_TEE_CORE_NB_CORE,2) 14$(call force,CFG_DRAM0_SIZE,0x40000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_SHMEM_SIZE ?= 0x00100000 17CFG_BOOT_SYNC_CPU ?= y 18CFG_BOOT_SECONDARY_REQUEST ?= y 19endif 20 21ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 22include core/arch/arm/cpu/cortex-a7.mk 23$(call force,CFG_TEE_CORE_NB_CORE,2) 24$(call force,CFG_DRAM0_SIZE,0x80000000) 25$(call force,CFG_CORE_CLUSTER_SHIFT,2) 26CFG_SHMEM_SIZE ?= 0x00100000 27CFG_BOOT_SYNC_CPU ?= y 28CFG_BOOT_SECONDARY_REQUEST ?= y 29endif 30 31ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 32include core/arch/arm/cpu/cortex-armv8-0.mk 33$(call force,CFG_TEE_CORE_NB_CORE,1) 34$(call force,CFG_DRAM0_SIZE,0x40000000) 35$(call force,CFG_CORE_CLUSTER_SHIFT,2) 36CFG_NUM_THREADS ?= 2 37CFG_SHMEM_SIZE ?= 0x00200000 38endif 39 40ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 41include core/arch/arm/cpu/cortex-armv8-0.mk 42$(call force,CFG_TEE_CORE_NB_CORE,4) 43$(call force,CFG_DRAM0_SIZE,0x80000000) 44$(call force,CFG_CORE_CLUSTER_SHIFT,2) 45CFG_SHMEM_SIZE ?= 0x00200000 46endif 47 48ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 49include core/arch/arm/cpu/cortex-armv8-0.mk 50$(call force,CFG_TEE_CORE_NB_CORE,4) 51$(call force,CFG_DRAM0_SIZE,0x80000000) 52$(call force,CFG_CORE_CLUSTER_SHIFT,2) 53CFG_SHMEM_SIZE ?= 0x00200000 54endif 55 56ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 57include core/arch/arm/cpu/cortex-armv8-0.mk 58$(call force,CFG_TEE_CORE_NB_CORE,8) 59$(call force,CFG_DRAM0_SIZE,0x80000000) 60$(call force,CFG_CORE_CLUSTER_SHIFT,2) 61$(call force,CFG_ARM_GICV3,y) 62CFG_SHMEM_SIZE ?= 0x00200000 63endif 64 65ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 66include core/arch/arm/cpu/cortex-armv8-0.mk 67$(call force,CFG_TEE_CORE_NB_CORE,8) 68$(call force,CFG_DRAM0_SIZE,0x80000000) 69$(call force,CFG_CORE_CLUSTER_SHIFT,1) 70$(call force,CFG_ARM_GICV3,y) 71CFG_SHMEM_SIZE ?= 0x00200000 72endif 73 74ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 75include core/arch/arm/cpu/cortex-armv8-0.mk 76$(call force,CFG_TEE_CORE_NB_CORE,16) 77$(call force,CFG_DRAM0_SIZE,0x80000000) 78$(call force,CFG_DRAM1_BASE,0x2080000000) 79$(call force,CFG_DRAM1_SIZE,0x1F80000000) 80$(call force,CFG_CORE_CLUSTER_SHIFT,1) 81$(call force,CFG_ARM_GICV3,y) 82$(call force,CFG_PL011,y) 83$(call force,CFG_CORE_ARM64_PA_BITS,48) 84$(call force,CFG_EMBED_DTB,y) 85$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 86CFG_LS_I2C ?= y 87CFG_LS_GPIO ?= y 88CFG_LS_DSPI ?= y 89CFG_SHMEM_SIZE ?= 0x00200000 90endif 91 92ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 93include core/arch/arm/cpu/cortex-armv8-0.mk 94$(call force,CFG_TEE_CORE_NB_CORE,16) 95$(call force,CFG_DRAM0_SIZE,0x80000000) 96$(call force,CFG_DRAM1_BASE,0x2080000000) 97$(call force,CFG_DRAM1_SIZE,0x1F80000000) 98$(call force,CFG_CORE_CLUSTER_SHIFT,1) 99$(call force,CFG_ARM_GICV3,y) 100$(call force,CFG_PL011,y) 101$(call force,CFG_CORE_ARM64_PA_BITS,48) 102$(call force,CFG_EMBED_DTB,y) 103$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 104CFG_LS_I2C ?= y 105CFG_LS_GPIO ?= y 106CFG_LS_DSPI ?= y 107CFG_SHMEM_SIZE ?= 0x00200000 108endif 109 110ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 111include core/arch/arm/cpu/cortex-armv8-0.mk 112$(call force,CFG_TEE_CORE_NB_CORE,2) 113$(call force,CFG_DRAM0_SIZE,0x80000000) 114$(call force,CFG_CORE_CLUSTER_SHIFT,1) 115$(call force,CFG_ARM_GICV3,y) 116CFG_SHMEM_SIZE ?= 0x00200000 117endif 118 119ifeq ($(platform-flavor-armv8),1) 120$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 121CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 122CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 123#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 124CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 125$(call force,CFG_ARM64_core,y) 126CFG_USER_TA_TARGETS ?= ta_arm64 127else 128#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 129CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 130CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 131#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 132CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 133endif 134 135#Keeping Number of TEE thread equal to number of cores on the SoC 136CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 137 138ifneq ($(CFG_ARM64_core),y) 139$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 140endif 141 142CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 143 144# NXP CAAM support is not enabled by default and can be enabled 145# on the command line 146CFG_NXP_CAAM ?= n 147 148ifeq ($(CFG_NXP_CAAM),y) 149# If NXP CAAM Driver is supported, the Crypto Driver interfacing 150# it with generic crypto API can be enabled. 151CFG_CRYPTO_DRIVER ?= y 152CFG_CRYPTO_DRIVER_DEBUG ?= 0 153else 154$(call force,CFG_CRYPTO_DRIVER,n) 155$(call force,CFG_WITH_SOFTWARE_PRNG,y) 156endif 157 158# Cryptographic configuration 159include core/arch/arm/plat-ls/crypto_conf.mk 160