xref: /optee_os/core/arch/arm/plat-imx/registers/imx8m.h (revision 3f286c3b9c107cd0f765967b3d9c1cc3c563477d)
1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright 2017-2019 NXP
4  */
5 
6 #ifndef __IMX8M_H__
7 #define __IMX8M_H__
8 
9 #include <registers/imx8m-crm.h>
10 
11 #define GICD_BASE	0x38800000
12 #define GICR_BASE	0x38880000
13 #define UART1_BASE	0x30860000
14 #define UART2_BASE	0x30890000
15 #define UART3_BASE	0x30880000
16 #define UART4_BASE	0x30A60000
17 #define TZASC_BASE	0x32F80000
18 #define CAAM_BASE	0x30900000
19 #define CCM_BASE	0x30380000
20 #define ANATOP_BASE	0x30360000
21 #define IOMUXC_BASE	0x30330000
22 
23 #ifdef CFG_MX8MQ
24 #define DIGPROG_OFFSET	0x06c
25 #endif
26 #if defined(CFG_MX8MM) || defined(CFG_MX8MN)
27 #define DIGPROG_OFFSET	0x800
28 #endif
29 
30 #if defined(CFG_MX8MM)
31 #define I2C1_BASE		0x30a20000
32 #define I2C2_BASE		0x30a30000
33 #define I2C3_BASE		0x30a40000
34 
35 #define IOMUXC_I2C1_SCL_CFG_OFF	0x47C
36 #define IOMUXC_I2C1_SDA_CFG_OFF	0x480
37 #define IOMUXC_I2C1_SCL_MUX_OFF	0x214
38 #define IOMUXC_I2C1_SDA_MUX_OFF	0x218
39 #endif
40 
41 #endif /* __IMX8M_H__ */
42