1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef __IMX7ULP_H__ 7 #define __IMX7ULP_H__ 8 9 #define GIC_BASE 0x40020000 10 #define GIC_SIZE 0x8000 11 #define GICC_OFFSET 0x2000 12 #define GICD_OFFSET 0x1000 13 14 #define AIPS0_BASE 0x40000000 15 #define AIPS0_SIZE 0x800000 16 #define AIPS1_BASE 0x40800000 17 #define AIPS1_SIZE 0x800000 18 #define M4_AIPS_BASE 0x41000000 19 #define M4_AIPS_SIZE 0x100000 20 #define M4_AIPS0_BASE 0x41000000 21 #define M4_AIPS0_SIZE 0x80000 22 #define M4_AIPS1_BASE 0x41080000 23 #define M4_AIPS1_SIZE 0x80000 24 25 #define GPIOC_BASE 0x400f0000 26 #define GPIOD_BASE 0x400f0040 27 #define GPIOE_BASE 0x400f0080 28 #define GPIOF_BASE 0x400f00c0 29 #define TPM5_BASE 0x40260000 30 #define SCG1_BASE 0x403e0000 31 #define PCC2_BASE 0x403f0000 32 #define PMC1_BASE 0x40400000 33 #define SMC1_BASE 0x40410000 34 #define MMDC_BASE 0x40ab0000 35 #define IOMUXC1_BASE 0x40ac0000 36 #define MMDC_IO_BASE 0x40ad0000 37 #define PCC3_BASE 0x40b30000 38 #define PMC0_BASE 0x410a1000 39 #define SIM_BASE 0x410a3000 40 41 #define CAAM_BASE 0x40240000 42 #define UART4_BASE 0x402d0000 43 #define UART5_BASE 0x402e0000 44 #define UART6_BASE 0x40a60000 45 #define UART7_BASE 0x40a70000 46 47 #define IRAM_BASE 0x1FFFC000 48 #define IRAM_SIZE 0x4000 49 50 #define LP_OCRAM_START IRAM_BASE 51 52 #endif /* __IMX7ULP_H__ */ 53