1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 #ifndef __IMX7_H__ 6 #define __IMX7_H__ 7 8 #include <registers/imx7-crm_regs.h> 9 10 #define GIC_BASE 0x31000000 11 #define GIC_SIZE 0x8000 12 #define GICC_OFFSET 0x2000 13 #define GICD_OFFSET 0x1000 14 15 #define CAAM_BASE 0x30900000 16 #define UART1_BASE 0x30860000 17 #define UART2_BASE 0x30890000 18 #define UART3_BASE 0x30880000 19 #define UART4_BASE 0x30A60000 20 #define UART5_BASE 0x30A70000 21 22 #define AIPS1_BASE 0x30000000 23 #define AIPS1_SIZE 0x400000 24 #define AIPS2_BASE 0x30400000 25 #define AIPS2_SIZE 0x400000 26 #define AIPS3_BASE 0x30800000 27 #define AIPS3_SIZE 0x400000 28 29 #define WDOG_BASE 0x30280000 30 #define LPSR_BASE 0x30270000 31 #define IOMUXC_BASE 0x30330000 32 #define IOMUXC_GPR_BASE 0x30340000 33 #define OCOTP_BASE 0x30350000 34 #define ANATOP_BASE 0x30360000 35 #define SNVS_BASE 0x30370000 36 #define CCM_BASE 0x30380000 37 #define SRC_BASE 0x30390000 38 #define GPC_BASE 0x303A0000 39 #define CSU_BASE 0x303E0000 40 #define TZASC_BASE 0x30780000 41 #define DDRC_PHY_BASE 0x30790000 42 #define MMDC_P0_BASE 0x307A0000 43 #define DDRC_BASE 0x307A0000 44 #define IRAM_BASE 0x00900000 45 #define IRAM_S_BASE 0x00180000 46 47 #define CSU_CSL_START 0x0 48 #define CSU_CSL_END 0x100 49 #define CSU_ACCESS_ALL 0x00FF00FF 50 #define CSU_SETTING_LOCK 0x01000100 51 52 #define TRUSTZONE_OCRAM_START 0x180000 53 54 #define IOMUXC_GPR9_OFFSET 0x24 55 #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 56 57 #define IOMUXC_GPR11_OFFSET 0x2C 58 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 59 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 60 61 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 62 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 63 64 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 65 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 66 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 67 68 #define DIGPROG_OFFSET 0x800 69 70 #endif /* __IMX7_H__ */ 71