1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 #ifndef __IMX7_H__ 6 #define __IMX7_H__ 7 8 #define GIC_BASE 0x31000000 9 #define GIC_SIZE 0x8000 10 #define GICC_OFFSET 0x2000 11 #define GICD_OFFSET 0x1000 12 13 #define CAAM_BASE 0x30900000 14 #define UART1_BASE 0x30860000 15 #define UART2_BASE 0x30890000 16 #define UART3_BASE 0x30880000 17 #define UART4_BASE 0x30A60000 18 #define UART5_BASE 0x30A70000 19 20 #define AIPS1_BASE 0x30000000 21 #define AIPS1_SIZE 0x400000 22 #define AIPS2_BASE 0x30400000 23 #define AIPS2_SIZE 0x400000 24 #define AIPS3_BASE 0x30800000 25 #define AIPS3_SIZE 0x400000 26 27 #define WDOG_BASE 0x30280000 28 #define LPSR_BASE 0x30270000 29 #define IOMUXC_BASE 0x30330000 30 #define IOMUXC_GPR_BASE 0x30340000 31 #define OCOTP_BASE 0x30350000 32 #define ANATOP_BASE 0x30360000 33 #define SNVS_BASE 0x30370000 34 #define CCM_BASE 0x30380000 35 #define SRC_BASE 0x30390000 36 #define GPC_BASE 0x303A0000 37 #define CSU_BASE 0x303E0000 38 #define TZASC_BASE 0x30780000 39 #define DDRC_PHY_BASE 0x30790000 40 #define MMDC_P0_BASE 0x307A0000 41 #define DDRC_BASE 0x307A0000 42 #define IRAM_BASE 0x00900000 43 #define IRAM_S_BASE 0x00180000 44 45 #define CSU_CSL_START 0x0 46 #define CSU_CSL_END 0x100 47 #define CSU_ACCESS_ALL 0x00FF00FF 48 #define CSU_SETTING_LOCK 0x01000100 49 50 #define TRUSTZONE_OCRAM_START 0x180000 51 52 #define IOMUXC_GPR9_OFFSET 0x24 53 #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 54 55 #define IOMUXC_GPR11_OFFSET 0x2C 56 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 57 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 58 59 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 60 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 61 62 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 63 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 64 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 65 66 #define DIGPROG_OFFSET 0x800 67 68 #endif /* __IMX7_H__ */ 69