1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2017-2020 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __IMX6_H__ 31 #define __IMX6_H__ 32 33 #include <registers/imx6-crm.h> 34 #include <registers/imx6-dcp.h> 35 36 #define UART1_BASE 0x2020000 37 #define IOMUXC_BASE 0x020E0000 38 #define IOMUXC_SIZE 0x4000 39 #define IOMUXC_GPR_BASE 0x020E4000 40 #define SRC_BASE 0x020D8000 41 #define SRC_SIZE 0x4000 42 #define CCM_BASE 0x020C4000 43 #define CCM_SIZE 0x4000 44 #define ANATOP_BASE 0x020C8000 45 #define ANATOP_SIZE 0x1000 46 #define SNVS_BASE 0x020CC000 47 #define GPC_BASE 0x020DC000 48 #define GPC_SIZE 0x4000 49 #define WDOG_BASE 0x020BC000 50 #define CSU_BASE 0x021C0000 51 #define SEMA4_BASE 0x02290000 52 #define SEMA4_SIZE 0x4000 53 #define MMDC_P0_BASE 0x021B0000 54 #define MMDC_P0_SIZE 0x4000 55 #define MMDC_P1_BASE 0x021B4000 56 #define MMDC_P1_SIZE 0x4000 57 #define TZASC_BASE 0x21D0000 58 #define TZASC2_BASE 0x21D4000 59 #define UART2_BASE 0x021E8000 60 #define UART3_BASE 0x021EC000 61 #define UART4_BASE 0x021F0000 62 #define UART5_BASE 0x021F4000 63 #define AIPS1_BASE 0x02000000 64 #define AIPS1_SIZE 0x100000 65 #define AIPS2_BASE 0x02100000 66 #define AIPS2_SIZE 0x100000 67 #define AIPS3_BASE 0x02200000 68 #define AIPS3_SIZE 0x100000 69 70 #if defined(CFG_MX6ULL) 71 #define RNGB_BASE 0x02284000 72 #elif defined(CFG_MX6SL) || defined(CFG_MX6SLL) 73 #define RNGB_BASE 0x021b4000 74 #endif 75 76 #define SCU_BASE 0x00A00000 77 #define PL310_BASE 0x00A02000 78 #define SRC_BASE 0x020D8000 79 #define IRAM_BASE 0x00900000 80 81 #define OCOTP_BASE 0x021BC000 82 83 #define GIC_BASE 0x00A00000 84 #define GICD_OFFSET 0x1000 85 86 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) 87 #define GICC_OFFSET 0x2000 88 #define UART6_BASE 0x021FC000 89 #define UART7_BASE 0x02018000 90 /* No CAAM on i.MX6ULL */ 91 #define CAAM_BASE 0x02140000 92 #else 93 #define GICC_OFFSET 0x100 94 #define CAAM_BASE 0x02100000 95 #endif 96 97 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) 98 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) 99 100 /* Central Security Unit register values */ 101 #define CSU_CSL_START 0x0 102 #define CSU_CSL_END 0xA0 103 #define CSU_ACCESS_ALL 0x00FF00FF 104 #define CSU_SETTING_LOCK 0x01000100 105 #define CSU_SA 0x218 106 107 /* Used in suspend/resume and low power idle */ 108 #define MX6Q_SRC_GPR1 0x20 109 #define MX6Q_SRC_GPR2 0x24 110 #define MX6Q_MMDC_MISC 0x18 111 #define MX6Q_MMDC_MAPSR 0x404 112 #define MX6Q_MMDC_MPDGCTRL0 0x83c 113 #define MX6Q_GPC_IMR1 0x08 114 #define MX6Q_GPC_IMR2 0x0c 115 #define MX6Q_GPC_IMR3 0x10 116 #define MX6Q_GPC_IMR4 0x14 117 #define MX6Q_CCM_CCR 0x0 118 #define MX6Q_ANATOP_CORE 0x140 119 120 #define IOMUXC_GPR9_OFFSET 0x24 121 #define IOMUXC_GPR10_OFFSET 0x28 122 123 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET 5 124 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5) 125 126 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET 4 127 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4) 128 129 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET 20 130 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20) 131 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET 21 132 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21) 133 134 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET_6UL 11 135 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11) 136 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET_6UL 10 137 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10) 138 139 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET_6UL 26 140 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26) 141 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL (27) 142 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27) 143 144 #ifdef CFG_MX6SL 145 #define DIGPROG_OFFSET 0x280 146 #else 147 #define DIGPROG_OFFSET 0x260 148 #endif 149 150 #if defined(CFG_MX6ULL) 151 #define I2C1_BASE 0x021a0000 152 #define I2C2_BASE 0x021a4000 153 #define I2C3_BASE 0x021a8000 154 #define I2C4_BASE 0x021f8000 155 156 #define IOMUXC_I2C1_SCL_CFG_OFF 0x340 157 #define IOMUXC_I2C1_SDA_CFG_OFF 0x344 158 #define IOMUXC_I2C1_SCL_MUX_OFF 0xb4 159 #define IOMUXC_I2C1_SDA_MUX_OFF 0xb8 160 #define IOMUXC_I2C1_SCL_INP_OFF 0x5a4 161 #define IOMUXC_I2C1_SDA_INP_OFF 0x5a8 162 #endif 163 164 #endif /* __IMX6_H__ */ 165