1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/imx_uart.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <platform_config.h> 42 #include <stdint.h> 43 #include <sm/optee_smc.h> 44 #include <tee/entry_fast.h> 45 #include <tee/entry_std.h> 46 47 48 static void main_fiq(void); 49 static struct gic_data gic_data; 50 51 static const struct thread_handlers handlers = { 52 .std_smc = tee_entry_std, 53 .fast_smc = tee_entry_fast, 54 .nintr = main_fiq, 55 #if defined(CFG_WITH_ARM_TRUSTED_FW) 56 .cpu_on = cpu_on_handler, 57 .cpu_off = pm_do_nothing, 58 .cpu_suspend = pm_do_nothing, 59 .cpu_resume = pm_do_nothing, 60 .system_off = pm_do_nothing, 61 .system_reset = pm_do_nothing, 62 #else 63 .cpu_on = pm_panic, 64 .cpu_off = pm_panic, 65 .cpu_suspend = pm_panic, 66 .cpu_resume = pm_panic, 67 .system_off = pm_panic, 68 .system_reset = pm_panic, 69 #endif 70 }; 71 72 static struct imx_uart_data console_data; 73 74 #ifdef CONSOLE_UART_BASE 75 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 76 CORE_MMU_PGDIR_SIZE); 77 #endif 78 #ifdef GIC_BASE 79 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 80 #endif 81 #ifdef ANATOP_BASE 82 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 83 #endif 84 #ifdef GICD_BASE 85 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 86 #endif 87 #ifdef AIPS1_BASE 88 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 89 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 90 #endif 91 #ifdef AIPS2_BASE 92 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 93 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 94 #endif 95 #ifdef AIPS3_BASE 96 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 97 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 98 #endif 99 #ifdef IRAM_BASE 100 register_phys_mem(MEM_AREA_TEE_COHERENT, 101 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 102 CORE_MMU_PGDIR_SIZE); 103 #endif 104 #ifdef IRAM_S_BASE 105 register_phys_mem(MEM_AREA_TEE_COHERENT, 106 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 107 CORE_MMU_PGDIR_SIZE); 108 #endif 109 110 #if defined(CFG_PL310) 111 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 112 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 113 CORE_MMU_PGDIR_SIZE); 114 #endif 115 116 const struct thread_handlers *generic_boot_get_handlers(void) 117 { 118 return &handlers; 119 } 120 121 static void main_fiq(void) 122 { 123 gic_it_handle(&gic_data); 124 } 125 126 void console_init(void) 127 { 128 imx_uart_init(&console_data, CONSOLE_UART_BASE); 129 register_serial_console(&console_data.chip); 130 } 131 132 void main_init_gic(void) 133 { 134 #ifdef CFG_ARM_GICV3 135 vaddr_t gicd_base; 136 137 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 138 139 if (!gicd_base) 140 panic(); 141 142 /* Initialize GIC */ 143 gic_init(&gic_data, 0, gicd_base); 144 itr_init(&gic_data.chip); 145 #else 146 vaddr_t gicc_base; 147 vaddr_t gicd_base; 148 149 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 150 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 151 152 if (!gicc_base || !gicd_base) 153 panic(); 154 155 /* Initialize GIC */ 156 gic_init(&gic_data, gicc_base, gicd_base); 157 itr_init(&gic_data.chip); 158 #endif 159 } 160 161 #if defined(CFG_MX6Q) || defined(CFG_MX6D) || defined(CFG_MX6DL) || \ 162 defined(CFG_MX7) 163 void main_secondary_init_gic(void) 164 { 165 gic_cpu_init(&gic_data); 166 } 167 #endif 168