1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <imx.h> 36 #include <io.h> 37 #include <kernel/boot.h> 38 #include <kernel/interrupt.h> 39 #include <kernel/misc.h> 40 #include <kernel/panic.h> 41 #include <mm/core_memprot.h> 42 #include <mm/core_mmu.h> 43 #include <platform_config.h> 44 #include <sm/optee_smc.h> 45 #include <stdint.h> 46 47 static struct gic_data gic_data __nex_bss; 48 49 static struct imx_uart_data console_data __nex_bss; 50 51 #ifdef CONSOLE_UART_BASE 52 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 53 CORE_MMU_PGDIR_SIZE); 54 #endif 55 #ifdef GIC_BASE 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 57 #endif 58 #ifdef ANATOP_BASE 59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 60 #endif 61 #ifdef GICD_BASE 62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 63 #endif 64 #ifdef AIPS0_BASE 65 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE, 66 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE)); 67 #endif 68 #ifdef AIPS1_BASE 69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 70 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 71 #endif 72 #ifdef AIPS2_BASE 73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 74 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 75 #endif 76 #ifdef AIPS3_BASE 77 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 78 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 79 #endif 80 #ifdef IRAM_BASE 81 register_phys_mem(MEM_AREA_TEE_COHERENT, 82 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 83 CORE_MMU_PGDIR_SIZE); 84 #endif 85 #ifdef M4_AIPS_BASE 86 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE); 87 #endif 88 #ifdef IRAM_S_BASE 89 register_phys_mem(MEM_AREA_TEE_COHERENT, 90 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 91 CORE_MMU_PGDIR_SIZE); 92 #endif 93 94 #if defined(CFG_PL310) 95 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 96 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 97 CORE_MMU_PGDIR_SIZE); 98 #endif 99 100 register_dynamic_shm(CFG_NSEC_DDR_0_BASE, CFG_NSEC_DDR_0_SIZE); 101 #if defined(CFG_NSEC_DDR_1_BASE) && defined(CFG_NSEC_DDR_1_SIZE) 102 register_dynamic_shm(CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE); 103 #endif 104 105 void itr_core_handler(void) 106 { 107 gic_it_handle(&gic_data); 108 } 109 110 void console_init(void) 111 { 112 #ifdef CONSOLE_UART_BASE 113 imx_uart_init(&console_data, CONSOLE_UART_BASE); 114 register_serial_console(&console_data.chip); 115 #endif 116 } 117 118 void main_init_gic(void) 119 { 120 #ifdef CFG_ARM_GICV3 121 vaddr_t gicd_base; 122 123 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 124 125 if (!gicd_base) 126 panic(); 127 128 /* Initialize GIC */ 129 gic_init(&gic_data, 0, gicd_base); 130 itr_init(&gic_data.chip); 131 #else 132 vaddr_t gicc_base; 133 vaddr_t gicd_base; 134 135 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 136 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 137 138 if (!gicc_base || !gicd_base) 139 panic(); 140 141 /* Initialize GIC */ 142 gic_init(&gic_data, gicc_base, gicd_base); 143 itr_init(&gic_data.chip); 144 #endif 145 } 146 147 #if CFG_TEE_CORE_NB_CORE > 1 148 void main_secondary_init_gic(void) 149 { 150 gic_cpu_init(&gic_data); 151 } 152 #endif 153