1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019, 2023 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <imx.h> 36 #include <kernel/boot.h> 37 #include <mm/core_memprot.h> 38 #include <mm/core_mmu.h> 39 #include <platform_config.h> 40 #include <stdint.h> 41 42 static struct imx_uart_data console_data __nex_bss; 43 44 #ifdef CONSOLE_UART_BASE 45 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 46 CORE_MMU_PGDIR_SIZE); 47 #endif 48 #ifdef GIC_BASE 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 50 #endif 51 #ifdef ANATOP_BASE 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 53 #endif 54 #ifdef GICD_BASE 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 56 #endif 57 #ifdef AIPS0_BASE 58 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE, 59 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE)); 60 #endif 61 #ifdef AIPS1_BASE 62 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 63 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 64 #endif 65 #ifdef AIPS2_BASE 66 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 67 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 68 #endif 69 #ifdef AIPS3_BASE 70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 71 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 72 #endif 73 #ifdef IRAM_BASE 74 register_phys_mem(MEM_AREA_TEE_COHERENT, 75 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 76 CORE_MMU_PGDIR_SIZE); 77 #endif 78 #ifdef M4_AIPS_BASE 79 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE); 80 #endif 81 #ifdef IRAM_S_BASE 82 register_phys_mem(MEM_AREA_TEE_COHERENT, 83 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 84 CORE_MMU_PGDIR_SIZE); 85 #endif 86 87 #if defined(CFG_PL310) 88 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 89 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 90 CORE_MMU_PGDIR_SIZE); 91 #endif 92 93 #ifdef CFG_DRAM_BASE 94 register_ddr(CFG_DRAM_BASE, CFG_DDR_SIZE); 95 #endif 96 #ifdef CFG_NSEC_DDR_1_BASE 97 register_ddr(CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE); 98 #endif 99 100 void console_init(void) 101 { 102 #ifdef CONSOLE_UART_BASE 103 imx_uart_init(&console_data, CONSOLE_UART_BASE); 104 register_serial_console(&console_data.chip); 105 #endif 106 } 107 108 void boot_primary_init_intc(void) 109 { 110 #ifdef GICD_BASE 111 gic_init(0, GICD_BASE); 112 #else 113 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 114 #endif 115 } 116 117 #if CFG_TEE_CORE_NB_CORE > 1 118 void boot_secondary_init_intc(void) 119 { 120 gic_cpu_init(); 121 } 122 #endif 123