1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/imx_uart.h> 33 #include <io.h> 34 #include <kernel/generic_boot.h> 35 #include <kernel/misc.h> 36 #include <kernel/panic.h> 37 #include <kernel/pm_stubs.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 #include <sm/optee_smc.h> 43 #include <tee/entry_fast.h> 44 #include <tee/entry_std.h> 45 46 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 47 defined(PLATFORM_FLAVOR_mx6qsabresd) 48 #include <drivers/gic.h> 49 #include <kernel/tz_ssvce_pl310.h> 50 #endif 51 52 static void main_fiq(void); 53 54 static const struct thread_handlers handlers = { 55 .std_smc = tee_entry_std, 56 .fast_smc = tee_entry_fast, 57 .fiq = main_fiq, 58 .cpu_on = pm_panic, 59 .cpu_off = pm_panic, 60 .cpu_suspend = pm_panic, 61 .cpu_resume = pm_panic, 62 .system_off = pm_panic, 63 .system_reset = pm_panic, 64 }; 65 66 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 67 defined(PLATFORM_FLAVOR_mx6qsabresd) 68 static struct gic_data gic_data; 69 70 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 71 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 72 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 73 #endif 74 75 const struct thread_handlers *generic_boot_get_handlers(void) 76 { 77 return &handlers; 78 } 79 80 static void main_fiq(void) 81 { 82 panic(); 83 } 84 85 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 86 defined(PLATFORM_FLAVOR_mx6qsabresd) 87 void plat_cpu_reset_late(void) 88 { 89 uintptr_t addr; 90 91 if (!get_core_pos()) { 92 /* primary core */ 93 #if defined(CFG_BOOT_SECONDARY_REQUEST) 94 /* set secondary entry address and release core */ 95 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 8); 96 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 16); 97 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 24); 98 99 write32(SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR); 100 #endif 101 102 /* SCU config */ 103 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 104 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 105 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 106 107 /* SCU enable */ 108 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 109 SCU_BASE + SCU_CTRL); 110 111 /* configure imx6 CSU */ 112 113 /* first grant all peripherals */ 114 for (addr = CSU_BASE + CSU_CSL_START; 115 addr != CSU_BASE + CSU_CSL_END; 116 addr += 4) 117 write32(CSU_ACCESS_ALL, addr); 118 119 /* lock the settings */ 120 for (addr = CSU_BASE + CSU_CSL_START; 121 addr != CSU_BASE + CSU_CSL_END; 122 addr += 4) 123 write32(read32(addr) | CSU_SETTING_LOCK, addr); 124 } 125 } 126 #endif 127 128 static vaddr_t console_base(void) 129 { 130 static void *va; 131 132 if (cpu_mmu_enabled()) { 133 if (!va) 134 va = phys_to_virt(CONSOLE_UART_PA_BASE, 135 MEM_AREA_IO_NSEC); 136 return (vaddr_t)va; 137 } 138 return CONSOLE_UART_BASE; 139 } 140 141 void console_init(void) 142 { 143 vaddr_t base = console_base(); 144 145 imx_uart_init(base); 146 } 147 148 void console_putc(int ch) 149 { 150 vaddr_t base = console_base(); 151 152 /* If \n, also do \r */ 153 if (ch == '\n') 154 imx_uart_putc('\r', base); 155 imx_uart_putc(ch, base); 156 } 157 158 void console_flush(void) 159 { 160 vaddr_t base = console_base(); 161 162 imx_uart_flush_tx_fifo(base); 163 } 164 165 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 166 defined(PLATFORM_FLAVOR_mx6qsabresd) 167 vaddr_t pl310_base(void) 168 { 169 static void *va __early_bss; 170 171 if (cpu_mmu_enabled()) { 172 if (!va) 173 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 174 return (vaddr_t)va; 175 } 176 return PL310_BASE; 177 } 178 179 void main_init_gic(void) 180 { 181 vaddr_t gicc_base; 182 vaddr_t gicd_base; 183 184 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 185 MEM_AREA_IO_SEC); 186 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 187 MEM_AREA_IO_SEC); 188 189 if (!gicc_base || !gicd_base) 190 panic(); 191 192 /* Initialize GIC */ 193 gic_init(&gic_data, gicc_base, gicd_base); 194 itr_init(&gic_data.chip); 195 } 196 197 void main_secondary_init_gic(void) 198 { 199 gic_cpu_init(&gic_data); 200 } 201 #endif 202