1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <arm32.h> 31 #include <console.h> 32 #include <drivers/gic.h> 33 #include <drivers/imx_uart.h> 34 #include <io.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <kernel/pm_stubs.h> 39 #include <mm/core_mmu.h> 40 #include <mm/core_memprot.h> 41 #include <platform_config.h> 42 #include <stdint.h> 43 #include <sm/optee_smc.h> 44 #include <tee/entry_fast.h> 45 #include <tee/entry_std.h> 46 47 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 48 defined(PLATFORM_FLAVOR_mx6qsabresd) 49 #include <kernel/tz_ssvce_pl310.h> 50 #endif 51 52 static void main_fiq(void); 53 static struct gic_data gic_data; 54 55 static const struct thread_handlers handlers = { 56 .std_smc = tee_entry_std, 57 .fast_smc = tee_entry_fast, 58 .nintr = main_fiq, 59 .cpu_on = pm_panic, 60 .cpu_off = pm_panic, 61 .cpu_suspend = pm_panic, 62 .cpu_resume = pm_panic, 63 .system_off = pm_panic, 64 .system_reset = pm_panic, 65 }; 66 67 static struct imx_uart_data console_data __early_bss; 68 69 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 70 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 71 72 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 73 defined(PLATFORM_FLAVOR_mx6qsabresd) 74 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 75 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE); 76 #endif 77 78 const struct thread_handlers *generic_boot_get_handlers(void) 79 { 80 return &handlers; 81 } 82 83 static void main_fiq(void) 84 { 85 panic(); 86 } 87 88 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 89 defined(PLATFORM_FLAVOR_mx6qsabresd) 90 void plat_cpu_reset_late(void) 91 { 92 uintptr_t addr; 93 94 if (!get_core_pos()) { 95 /* primary core */ 96 #if defined(CFG_BOOT_SYNC_CPU) 97 /* set secondary entry address and release core */ 98 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 8); 99 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 16); 100 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 24); 101 102 write32(SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR); 103 #endif 104 105 /* SCU config */ 106 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC); 107 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC); 108 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC); 109 110 /* SCU enable */ 111 write32(read32(SCU_BASE + SCU_CTRL) | 0x1, 112 SCU_BASE + SCU_CTRL); 113 114 /* configure imx6 CSU */ 115 116 /* first grant all peripherals */ 117 for (addr = CSU_BASE + CSU_CSL_START; 118 addr != CSU_BASE + CSU_CSL_END; 119 addr += 4) 120 write32(CSU_ACCESS_ALL, addr); 121 122 /* lock the settings */ 123 for (addr = CSU_BASE + CSU_CSL_START; 124 addr != CSU_BASE + CSU_CSL_END; 125 addr += 4) 126 write32(read32(addr) | CSU_SETTING_LOCK, addr); 127 } 128 } 129 #endif 130 131 void console_init(void) 132 { 133 imx_uart_init(&console_data, CONSOLE_UART_BASE); 134 register_serial_console(&console_data.chip); 135 } 136 137 void main_init_gic(void) 138 { 139 vaddr_t gicc_base; 140 vaddr_t gicd_base; 141 142 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 143 MEM_AREA_IO_SEC); 144 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 145 MEM_AREA_IO_SEC); 146 147 if (!gicc_base || !gicd_base) 148 panic(); 149 150 /* Initialize GIC */ 151 gic_init(&gic_data, gicc_base, gicd_base); 152 itr_init(&gic_data.chip); 153 } 154 155 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 156 defined(PLATFORM_FLAVOR_mx6qsabresd) 157 vaddr_t pl310_base(void) 158 { 159 static void *va __early_bss; 160 161 if (cpu_mmu_enabled()) { 162 if (!va) 163 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 164 return (vaddr_t)va; 165 } 166 return PL310_BASE; 167 } 168 169 void main_secondary_init_gic(void) 170 { 171 gic_cpu_init(&gic_data); 172 } 173 #endif 174